Files
super6502/hw/fpga/output_files/super6502.cdf
Byron Lathi 3d9d340520 Get the FPGA part working
This changes some of the clocks, fixes a bug in the seven segment stuff.
2022-03-11 22:55:26 -06:00

14 lines
333 B
Mathematica

/* Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(10M50DAF484) Path("/home/byron/Projects/super6502/hw/fpga/output_files/") File("super6502.sof") MfrSpec(OpMask(1));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;