b48438f6b2
The write task will transmit a single byte, the puts task will transmit a string of length n. These do not do any verification, you still have to look at the output.
61 lines
906 B
Systemverilog
61 lines
906 B
Systemverilog
module testbench();
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timeunit 10ns;
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timeprecision 1ns;
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logic clk_50, clk, rst, cs;
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logic [1:0] addr;
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logic [7:0] data_in, data_out;
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logic rw;
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logic RXD, TXD;
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logic [7:0] status;
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uart dut(.*);
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always #1 clk_50 = clk_50 === 1'b0;
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always #100 clk = clk === 1'b0;
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task write(logic [7:0] data);
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@(negedge clk);
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cs <= '1;
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addr <= '0;
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data_in <= data;
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rw <= '0;
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@(negedge clk);
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cs <= '0;
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addr <= '0;
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data_in <= 8'hxx;
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rw <= '1;
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do begin
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@(negedge clk);
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cs <= '1;
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addr <= 1'b1;
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rw <= '1;
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@(negedge clk);
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end while (data_out != 8'h0);
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endtask
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task puts(string s, int n);
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for (int i = 0; i < n; i++)
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write(s[i]);
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endtask
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initial begin
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rst <= '1;
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repeat(5) @(posedge clk);
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rst <= '0;
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rw <= '1;
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cs <= '0;
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status <= '0;
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puts("Hello, world!\n", 14);
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$finish();
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end
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endmodule
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