bslathi19/super6502
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super6502/hw/fpga
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Byron Lathi 74210f57f7 Remove fpga RAM 
This removes the ram from inside the FPGA. All RAM is now located in the
external SDRAM instead.

The ROM is still in the FPGA to allow easier programming.
2022-03-21 14:01:16 -05:00
..
hvl
Remove fpga RAM
2022-03-21 14:01:16 -05:00
simulation/modelsim
Add irq status register
2022-03-14 13:16:09 -05:00
.gitignore
ignore .sopcinfo
2022-03-17 13:53:07 -05:00
addr_decode.sv
Remove fpga RAM
2022-03-21 14:01:16 -05:00
bb_spi_controller.sv
Add bb_spi_controller
2022-03-08 15:26:01 -06:00
board_io.sv
Add board-io, replace sevenseg in sw
2022-03-18 01:27:55 +00:00
cpu_clk.ppf
Add hex drivers
2022-03-11 18:25:55 -06:00
cpu_clk.qip
Add hex drivers
2022-03-11 18:25:55 -06:00
cpu_clk.v
Add hex drivers
2022-03-11 18:25:55 -06:00
HexDriver.sv
Add hex drivers
2022-03-11 18:25:55 -06:00
rom.qip
Add boot rom
2022-03-05 18:12:27 -06:00
rom.v
Get the FPGA part working
2022-03-11 22:55:26 -06:00
sdram_platform.qsys
Add SDRAM controller (controller)
2022-03-17 13:31:56 -05:00
sdram.sv
Move SDRAM and state machine into its own file
2022-03-17 17:49:20 -05:00
SevenSeg.sv
Implement enable byte in hw
2022-03-12 21:45:30 -06:00
super6502.qpf
Create quartus project
2022-03-05 16:38:12 -06:00
super6502.qsf
Remove fpga RAM
2022-03-21 14:01:16 -05:00
super6502.sdc
Move SDRAM and state machine into its own file
2022-03-17 17:49:20 -05:00
super6502.sv
Remove fpga RAM
2022-03-21 14:01:16 -05:00
uart.sv
Add receive logic to UART
2022-03-14 16:41:59 -05:00