bslathi19/super6502
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b48438f6b2949688b9a41028afd2ba0f9bdb4cb2
super6502/hw/fpga
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Byron Lathi b48438f6b2 Add write and puts tasks to the uart testbench 
The write task will transmit a single byte, the puts task will transmit
a string of length n. These do not do any verification, you still have
to look at the output.
2022-03-14 00:04:04 -05:00
..
greybox_tmp
Get the FPGA part working
2022-03-11 22:55:26 -06:00
hvl
Add write and puts tasks to the uart testbench
2022-03-14 00:04:04 -05:00
output_files
Don't track vcd files either
2022-03-12 19:34:43 -06:00
simulation/modelsim
Add write and puts tasks to the uart testbench
2022-03-14 00:04:04 -05:00
.gitignore
Clean up modelsim folder
2022-03-12 19:41:08 -06:00
addr_decode.sv
Add high pair of seven segment displays
2022-03-12 21:24:37 -06:00
bb_spi_controller.sv
Add bb_spi_controller
2022-03-08 15:26:01 -06:00
cpu_clk.ppf
Add hex drivers
2022-03-11 18:25:55 -06:00
cpu_clk.qip
Add hex drivers
2022-03-11 18:25:55 -06:00
cpu_clk.v
Add hex drivers
2022-03-11 18:25:55 -06:00
HexDriver.sv
Add hex drivers
2022-03-11 18:25:55 -06:00
ram.qip
Create quartus project
2022-03-05 17:52:42 -06:00
ram.v
Create quartus project
2022-03-05 17:52:42 -06:00
rom.qip
Add boot rom
2022-03-05 18:12:27 -06:00
rom.v
Get the FPGA part working
2022-03-11 22:55:26 -06:00
SevenSeg.sv
Implement enable byte in hw
2022-03-12 21:45:30 -06:00
super6502.qpf
Create quartus project
2022-03-05 16:38:12 -06:00
super6502.qsf
Add basic UART device
2022-03-13 19:42:41 -05:00
super6502.sdc
Get the FPGA part working
2022-03-11 22:55:26 -06:00
super6502.sv
Add basic UART device
2022-03-13 19:42:41 -05:00
uart.sv
Refactor uart.sv to better allow cpu control
2022-03-14 00:00:55 -05:00