Byron Lathi b4ff993080 Merge branch 'first_start' into 'master' ...

Get the FPGA part working

See merge request bslathi19/super6502!1

2022-03-13 01:44:41 +00:00

hw

Clean up modelsim folder

2022-03-12 19:41:08 -06:00

sw

Remove C tests

2022-03-12 19:25:01 -06:00

.gitlab-ci.yml

Update .gitlab-ci.yml

2022-03-10 22:27:43 +00:00

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5.5 MiB

Languages

SystemVerilog 47.7%

Verilog 41.8%

Python 4.8%

VHDL 2%

Assembly 2%

Other 1.6%