b8161e3082
The Logic analyzer isn't that useful anyway since it does not track rising and falling edges.
12 lines
202 B
Systemverilog
12 lines
202 B
Systemverilog
module addr_decode
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(
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input [15:0] i_addr,
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output o_rom_cs,
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output o_leds_cs
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);
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assign o_rom_cs = i_addr >= 16'hf000 && i_addr <= 16'hffff;
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assign o_leds_cs = i_addr == 16'hefff;
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endmodule |