Byron Lathi c6bf29649a Add some CLCs before ADCs

2023-10-29 19:47:15 -07:00

doc

Finish block diagram

2023-10-16 22:15:54 -07:00

hw

Up sim time

2023-10-26 21:54:08 -07:00

sw

Add some CLCs before ADCs

2023-10-29 19:47:15 -07:00

.gitignore

Start spi controller and tb

2023-07-21 22:10:39 -07:00

.gitlab-ci.yml

Upload filesystem image as well

2023-10-26 20:40:00 -07:00

.gitmodules

Resolve "Use dependencies instead of makefile chaining"

2023-09-30 04:16:52 +00:00

init_env.sh

Resolve "Run simulation as part of ci"

2023-09-30 05:05:12 +00:00

Description

No description provided

5.5 MiB

Languages

SystemVerilog 47.7%

Verilog 41.8%

Python 4.8%

VHDL 2%

Assembly 2%

Other 1.6%