Byron Lathi d113498459 Try a bad commit

2023-09-28 21:28:39 -07:00

hw

Try a bad commit

2023-09-28 21:28:39 -07:00

sw

Remove unneeded CR

2023-09-27 23:03:22 -07:00

.gitignore

Start spi controller and tb

2023-07-21 22:10:39 -07:00

.gitmodules

Add submodule back

2023-09-23 09:59:39 -07:00

init_env.sh

Add REPO_TOP env var

2023-09-24 10:35:17 -07:00

Description

No description provided

5.5 MiB

Languages

SystemVerilog 47.7%

Verilog 41.8%

Python 4.8%

VHDL 2%

Assembly 2%

Other 1.6%