7 lines
244 B
Plaintext
7 lines
244 B
Plaintext
[submodule "sw/cc65"]
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path = sw/cc65
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url = https://git.byronlathi.com/bslathi19/cc65
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[submodule "hw/efinix_fpga/simulation/verilog-6502"]
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path = hw/efinix_fpga/simulation/verilog-6502
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url = https://git.byronlathi.com/bslathi19/verilog-6502
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