Add sim cpu

2023-09-18 23:27:54 -07:00
parent b30e4c73fb
commit d37e32ec64
3 changed files with 16 additions and 0 deletions
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,3 +1,6 @@
 [submodule "sw/cc65"]
 	path = sw/cc65
 	url = https://git.byronlathi.com/bslathi19/cc65
+[submodule "hw/efinix_fpga/simulation/verilog-6502"]
+	path = hw/efinix_fpga/simulation/verilog-6502
+	url = https://git.byronlathi.com/bslathi19/verilog-6502
--- a/hw/efinix_fpga/simulation/sim_top.sv
+++ b/hw/efinix_fpga/simulation/sim_top.sv
@@ -0,0 +1,12 @@
+module sim_top();
+
+//TODO: this
+cpu_65c02 u_cpu();
+
+//TODO: also this
+super6502 u_dut();
+
+//TODO: decide what to do here
+memory u_mem();
+
+endmodule
--- a/hw/efinix_fpga/simulation/verilog-6502
+++ b/hw/efinix_fpga/simulation/verilog-6502