Byron Lathi da2675a3fe Reduce sim time for full sim

2023-11-18 16:43:19 -08:00

doc

Update diagram again

2023-10-31 23:11:19 -07:00

hw

Reduce sim time for full sim

2023-11-18 16:43:19 -08:00

sw

Add back long string

2023-10-30 00:04:57 -07:00

.gitignore

Start spi controller and tb

2023-07-21 22:10:39 -07:00

.gitlab-ci.yml

Fix level triggered test, add to ci

2023-11-16 08:14:58 -08:00

.gitmodules

Resolve "Use dependencies instead of makefile chaining"

2023-09-30 04:16:52 +00:00

init_env.sh

Resolve "Run simulation as part of ci"

2023-09-30 05:05:12 +00:00

Description

No description provided

5.5 MiB

Languages

SystemVerilog 47.7%

Verilog 41.8%

Python 4.8%

VHDL 2%

Assembly 2%

Other 1.6%