e063e9f6a3
So far the device only transmits the ASCII set on repeat, but will become fully featured later.
25 lines
328 B
Systemverilog
25 lines
328 B
Systemverilog
module testbench();
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timeunit 10ns;
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timeprecision 1ns;
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logic clk_50, clk, rst, cs;
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logic [1:0] addr;
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logic [7:0] data_in, data_out;
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logic rw;
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logic RXD, TXD;
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uart dut(.*);
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always #1 clk_50 = clk_50 === 1'b0;
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initial begin
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rst <= '1;
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repeat(5) @(posedge clk_50);
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rst <= '0;
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@(posedge clk_50);
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end
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endmodule
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