Files
super6502/hw/fpga/simulation/modelsim/uart.do
Byron Lathi e063e9f6a3 Add basic UART device
So far the device only transmits the ASCII set on repeat, but will
become fully featured later.
2022-03-13 19:42:41 -05:00

15 lines
455 B
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if {[file exists rtl_work]} {
vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work
vlog -sv -work work {../../uart.sv}
vlog -sv -work work {../../hvl/uart_testbench.sv}
vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L stratixv_ver -L stratixv_hssi_ver -L stratixv_pcie_hip_ver -L rtl_work -L work -voptargs="+acc" testbench
add wave -group {dut} -radix hexadecimal sim:/testbench/dut/*