Byron Lathi e73c4e1d08 Rewrite readblock in assembly

2023-08-08 19:28:10 -07:00

hw

Rewrite readblock in assembly

2023-08-08 19:28:10 -07:00

sw

Rewrite readblock in assembly

2023-08-08 19:28:10 -07:00

.gitignore

Start spi controller and tb

2023-07-21 22:10:39 -07:00

.gitmodules

Use our own toolchain instead of the one in the image

2022-04-20 12:41:20 -05:00

Description

No description provided

5.5 MiB

Languages

SystemVerilog 47.7%

Verilog 41.8%

Python 4.8%

VHDL 2%

Assembly 2%

Other 1.6%