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ed18b381f3970b5a58fdd618eaf8d1ba88cd546a
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Byron Lathi ed18b381f3 Change "clkdiv" to "tx_clkdiv"
2022-03-14 15:22:18 -05:00
hw
Change "clkdiv" to "tx_clkdiv"
2022-03-14 15:22:18 -05:00
sw
Add UART interrupts
2022-03-14 14:57:45 -05:00
.gitlab-ci.yml
Update .gitlab-ci.yml
2022-03-10 22:27:43 +00:00
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5.5 MiB
Languages
SystemVerilog 47.7%
Verilog 41.8%
Python 4.8%
VHDL 2%
Assembly 2%
Other 1.6%