bslathi19/super6502
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ee97c4cbaa4b01e23fd6e86b074a09cd4cf9c8b9
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Byron Lathi ee97c4cbaa Add platform generation to build stage
2022-03-17 14:25:26 -05:00
hw
ignore .sopcinfo
2022-03-17 13:53:07 -05:00
sw
Create SDRAM memory region
2022-03-17 13:37:34 -05:00
.gitlab-ci.yml
Add platform generation to build stage
2022-03-17 14:25:26 -05:00
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5.5 MiB
Languages
SystemVerilog 47.7%
Verilog 41.8%
Python 4.8%
VHDL 2%
Assembly 2%
Other 1.6%