bslathi19/super6502
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f8da9206d960de13d50014b36df00260e2972641
super6502/hw/fpga
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Byron Lathi f8da9206d9 Refactor uart.sv to better allow cpu control 
Added new signal tx_flag, which indicates whether the transmitter is
ready for new data.

Added status register, which when read will return the tx_flag bit, as
well as others that can be implemented.

Added new state IDLE, which resets the TX flag and allows new data to be
written.

Added code to allow for different baud rates, though it is still fixed
currently.
2022-03-14 00:00:55 -05:00
..
greybox_tmp
Get the FPGA part working
2022-03-11 22:55:26 -06:00
hvl
Add basic UART device
2022-03-13 19:42:41 -05:00
output_files
Don't track vcd files either
2022-03-12 19:34:43 -06:00
simulation/modelsim
Add basic UART device
2022-03-13 19:42:41 -05:00
.gitignore
Clean up modelsim folder
2022-03-12 19:41:08 -06:00
addr_decode.sv
Add high pair of seven segment displays
2022-03-12 21:24:37 -06:00
bb_spi_controller.sv
Add bb_spi_controller
2022-03-08 15:26:01 -06:00
cpu_clk.ppf
Add hex drivers
2022-03-11 18:25:55 -06:00
cpu_clk.qip
Add hex drivers
2022-03-11 18:25:55 -06:00
cpu_clk.v
Add hex drivers
2022-03-11 18:25:55 -06:00
HexDriver.sv
Add hex drivers
2022-03-11 18:25:55 -06:00
ram.qip
Create quartus project
2022-03-05 17:52:42 -06:00
ram.v
Create quartus project
2022-03-05 17:52:42 -06:00
rom.qip
Add boot rom
2022-03-05 18:12:27 -06:00
rom.v
Get the FPGA part working
2022-03-11 22:55:26 -06:00
SevenSeg.sv
Implement enable byte in hw
2022-03-12 21:45:30 -06:00
super6502.qpf
Create quartus project
2022-03-05 16:38:12 -06:00
super6502.qsf
Add basic UART device
2022-03-13 19:42:41 -05:00
super6502.sdc
Get the FPGA part working
2022-03-11 22:55:26 -06:00
super6502.sv
Add basic UART device
2022-03-13 19:42:41 -05:00
uart.sv
Refactor uart.sv to better allow cpu control
2022-03-14 00:00:55 -05:00