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Byron Lathi fd87d5b0ba Change to using includes rather than children
2022-03-05 19:08:42 -06:00
hw
Add fpga ci
2022-03-05 19:00:06 -06:00
sw
Add ci
2022-03-05 18:57:19 -06:00
.gitlab-ci.yml
Change to using includes rather than children
2022-03-05 19:08:42 -06:00
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5.5 MiB
Languages
SystemVerilog 47.7%
Verilog 41.8%
Python 4.8%
VHDL 2%
Assembly 2%
Other 1.6%