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eth: Update example designs

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-10-02 16:11:07 -07:00
parent 76d4465081
commit 159c9d6241
45 changed files with 1561 additions and 1296 deletions
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158
src/eth/example/HTG9200/fpga/rtl/fpga.sv
View File

@@ -66,90 +66,90 @@ module fpga #
/*
* Ethernet: QSFP28
*/
output wire logic [3:0] qsfp_1_tx_p,
output wire logic [3:0] qsfp_1_tx_n,
input wire logic [3:0] qsfp_1_rx_p,
input wire logic [3:0] qsfp_1_rx_n,
output wire logic qsfp_1_tx_p[4],
output wire logic qsfp_1_tx_n[4],
input wire logic qsfp_1_rx_p[4],
input wire logic qsfp_1_rx_n[4],
input wire logic qsfp_1_mgt_refclk_p,
input wire logic qsfp_1_mgt_refclk_n,
output wire logic qsfp_1_resetl,
input wire logic qsfp_1_modprsl,
input wire logic qsfp_1_intl,
output wire logic [3:0] qsfp_2_tx_p,
output wire logic [3:0] qsfp_2_tx_n,
input wire logic [3:0] qsfp_2_rx_p,
input wire logic [3:0] qsfp_2_rx_n,
output wire logic qsfp_2_tx_p[4],
output wire logic qsfp_2_tx_n[4],
input wire logic qsfp_2_rx_p[4],
input wire logic qsfp_2_rx_n[4],
input wire logic qsfp_2_mgt_refclk_p,
input wire logic qsfp_2_mgt_refclk_n,
output wire logic qsfp_2_resetl,
input wire logic qsfp_2_modprsl,
input wire logic qsfp_2_intl,
output wire logic [3:0] qsfp_3_tx_p,
output wire logic [3:0] qsfp_3_tx_n,
input wire logic [3:0] qsfp_3_rx_p,
input wire logic [3:0] qsfp_3_rx_n,
output wire logic qsfp_3_tx_p[4],
output wire logic qsfp_3_tx_n[4],
input wire logic qsfp_3_rx_p[4],
input wire logic qsfp_3_rx_n[4],
input wire logic qsfp_3_mgt_refclk_p,
input wire logic qsfp_3_mgt_refclk_n,
output wire logic qsfp_3_resetl,
input wire logic qsfp_3_modprsl,
input wire logic qsfp_3_intl,
output wire logic [3:0] qsfp_4_tx_p,
output wire logic [3:0] qsfp_4_tx_n,
input wire logic [3:0] qsfp_4_rx_p,
input wire logic [3:0] qsfp_4_rx_n,
output wire logic qsfp_4_tx_p[4],
output wire logic qsfp_4_tx_n[4],
input wire logic qsfp_4_rx_p[4],
input wire logic qsfp_4_rx_n[4],
input wire logic qsfp_4_mgt_refclk_p,
input wire logic qsfp_4_mgt_refclk_n,
output wire logic qsfp_4_resetl,
input wire logic qsfp_4_modprsl,
input wire logic qsfp_4_intl,
output wire logic [3:0] qsfp_5_tx_p,
output wire logic [3:0] qsfp_5_tx_n,
input wire logic [3:0] qsfp_5_rx_p,
input wire logic [3:0] qsfp_5_rx_n,
output wire logic qsfp_5_tx_p[4],
output wire logic qsfp_5_tx_n[4],
input wire logic qsfp_5_rx_p[4],
input wire logic qsfp_5_rx_n[4],
input wire logic qsfp_5_mgt_refclk_p,
input wire logic qsfp_5_mgt_refclk_n,
output wire logic qsfp_5_resetl,
input wire logic qsfp_5_modprsl,
input wire logic qsfp_5_intl,
output wire logic [3:0] qsfp_6_tx_p,
output wire logic [3:0] qsfp_6_tx_n,
input wire logic [3:0] qsfp_6_rx_p,
input wire logic [3:0] qsfp_6_rx_n,
output wire logic qsfp_6_tx_p[4],
output wire logic qsfp_6_tx_n[4],
input wire logic qsfp_6_rx_p[4],
input wire logic qsfp_6_rx_n[4],
input wire logic qsfp_6_mgt_refclk_p,
input wire logic qsfp_6_mgt_refclk_n,
output wire logic qsfp_6_resetl,
input wire logic qsfp_6_modprsl,
input wire logic qsfp_6_intl,
output wire logic [3:0] qsfp_7_tx_p,
output wire logic [3:0] qsfp_7_tx_n,
input wire logic [3:0] qsfp_7_rx_p,
input wire logic [3:0] qsfp_7_rx_n,
output wire logic qsfp_7_tx_p[4],
output wire logic qsfp_7_tx_n[4],
input wire logic qsfp_7_rx_p[4],
input wire logic qsfp_7_rx_n[4],
input wire logic qsfp_7_mgt_refclk_p,
input wire logic qsfp_7_mgt_refclk_n,
output wire logic qsfp_7_resetl,
input wire logic qsfp_7_modprsl,
input wire logic qsfp_7_intl,
output wire logic [3:0] qsfp_8_tx_p,
output wire logic [3:0] qsfp_8_tx_n,
input wire logic [3:0] qsfp_8_rx_p,
input wire logic [3:0] qsfp_8_rx_n,
output wire logic qsfp_8_tx_p[4],
output wire logic qsfp_8_tx_n[4],
input wire logic qsfp_8_rx_p[4],
input wire logic qsfp_8_rx_n[4],
input wire logic qsfp_8_mgt_refclk_p,
input wire logic qsfp_8_mgt_refclk_n,
output wire logic qsfp_8_resetl,
input wire logic qsfp_8_modprsl,
input wire logic qsfp_8_intl,
output wire logic [3:0] qsfp_9_tx_p,
output wire logic [3:0] qsfp_9_tx_n,
input wire logic [3:0] qsfp_9_rx_p,
input wire logic [3:0] qsfp_9_rx_n,
output wire logic qsfp_9_tx_p[4],
output wire logic qsfp_9_tx_n[4],
input wire logic qsfp_9_rx_p[4],
input wire logic qsfp_9_rx_n[4],
input wire logic qsfp_9_mgt_refclk_p,
input wire logic qsfp_9_mgt_refclk_n,
output wire logic qsfp_9_resetl,
@@ -320,6 +320,14 @@ localparam GTY_QUAD_CNT = PORT_CNT;
localparam GTY_CNT = GTY_QUAD_CNT*4;
localparam GTY_CLK_CNT = GTY_QUAD_CNT;
wire eth_gty_tx_p[GTY_CNT];
wire eth_gty_tx_n[GTY_CNT];
wire eth_gty_rx_p[GTY_CNT];
wire eth_gty_rx_n[GTY_CNT];
wire eth_gty_mgt_refclk_p[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_n[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_out[GTY_CLK_CNT];
assign clk_gty2_fdec = 1'b0;
assign clk_gty2_finc = 1'b0;
assign clk_gty2_oe_n = 1'b0;
@@ -328,6 +336,70 @@ assign clk_gty2_rst_n = !rst_125mhz_int;
wire eth_pll_locked = clk_gty2_lol_n;
assign qsfp_1_tx_p = eth_gty_tx_p[4*0 +: 4];
assign qsfp_1_tx_n = eth_gty_tx_n[4*0 +: 4];
assign eth_gty_rx_p[4*0 +: 4] = qsfp_1_rx_p;
assign eth_gty_rx_n[4*0 +: 4] = qsfp_1_rx_n;
assign qsfp_2_tx_p = eth_gty_tx_p[4*1 +: 4];
assign qsfp_2_tx_n = eth_gty_tx_n[4*1 +: 4];
assign eth_gty_rx_p[4*1 +: 4] = qsfp_2_rx_p;
assign eth_gty_rx_n[4*1 +: 4] = qsfp_2_rx_n;
assign qsfp_3_tx_p = eth_gty_tx_p[4*2 +: 4];
assign qsfp_3_tx_n = eth_gty_tx_n[4*2 +: 4];
assign eth_gty_rx_p[4*2 +: 4] = qsfp_3_rx_p;
assign eth_gty_rx_n[4*2 +: 4] = qsfp_3_rx_n;
assign qsfp_4_tx_p = eth_gty_tx_p[4*3 +: 4];
assign qsfp_4_tx_n = eth_gty_tx_n[4*3 +: 4];
assign eth_gty_rx_p[4*3 +: 4] = qsfp_4_rx_p;
assign eth_gty_rx_n[4*3 +: 4] = qsfp_4_rx_n;
assign qsfp_5_tx_p = eth_gty_tx_p[4*4 +: 4];
assign qsfp_5_tx_n = eth_gty_tx_n[4*4 +: 4];
assign eth_gty_rx_p[4*4 +: 4] = qsfp_5_rx_p;
assign eth_gty_rx_n[4*4 +: 4] = qsfp_5_rx_n;
assign qsfp_6_tx_p = eth_gty_tx_p[4*5 +: 4];
assign qsfp_6_tx_n = eth_gty_tx_n[4*5 +: 4];
assign eth_gty_rx_p[4*5 +: 4] = qsfp_6_rx_p;
assign eth_gty_rx_n[4*5 +: 4] = qsfp_6_rx_n;
assign qsfp_7_tx_p = eth_gty_tx_p[4*6 +: 4];
assign qsfp_7_tx_n = eth_gty_tx_n[4*6 +: 4];
assign eth_gty_rx_p[4*6 +: 4] = qsfp_7_rx_p;
assign eth_gty_rx_n[4*6 +: 4] = qsfp_7_rx_n;
assign qsfp_8_tx_p = eth_gty_tx_p[4*7 +: 4];
assign qsfp_8_tx_n = eth_gty_tx_n[4*7 +: 4];
assign eth_gty_rx_p[4*7 +: 4] = qsfp_8_rx_p;
assign eth_gty_rx_n[4*7 +: 4] = qsfp_8_rx_n;
assign qsfp_9_tx_p = eth_gty_tx_p[4*8 +: 4];
assign qsfp_9_tx_n = eth_gty_tx_n[4*8 +: 4];
assign eth_gty_rx_p[4*8 +: 4] = qsfp_9_rx_p;
assign eth_gty_rx_n[4*8 +: 4] = qsfp_9_rx_n;
assign eth_gty_mgt_refclk_p[0] = qsfp_1_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[0] = qsfp_1_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[1] = qsfp_2_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[1] = qsfp_2_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[2] = qsfp_3_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[2] = qsfp_3_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[3] = qsfp_4_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[3] = qsfp_4_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[4] = qsfp_5_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[4] = qsfp_5_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[5] = qsfp_6_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[5] = qsfp_6_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[6] = qsfp_7_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[6] = qsfp_7_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[7] = qsfp_8_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[7] = qsfp_8_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[8] = qsfp_9_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[8] = qsfp_9_mgt_refclk_n;
fpga_core #(
.SIM(SIM),
.VENDOR(VENDOR),
@@ -375,13 +447,13 @@ core_inst (
*/
.eth_pll_locked(eth_pll_locked),
.eth_gty_tx_p({qsfp_9_tx_p, qsfp_8_tx_p, qsfp_7_tx_p, qsfp_6_tx_p, qsfp_5_tx_p, qsfp_4_tx_p, qsfp_3_tx_p, qsfp_2_tx_p, qsfp_1_tx_p}),
.eth_gty_tx_n({qsfp_9_tx_n, qsfp_8_tx_n, qsfp_7_tx_n, qsfp_6_tx_n, qsfp_5_tx_n, qsfp_4_tx_n, qsfp_3_tx_n, qsfp_2_tx_n, qsfp_1_tx_n}),
.eth_gty_rx_p({qsfp_9_rx_p, qsfp_8_rx_p, qsfp_7_rx_p, qsfp_6_rx_p, qsfp_5_rx_p, qsfp_4_rx_p, qsfp_3_rx_p, qsfp_2_rx_p, qsfp_1_rx_p}),
.eth_gty_rx_n({qsfp_9_rx_n, qsfp_8_rx_n, qsfp_7_rx_n, qsfp_6_rx_n, qsfp_5_rx_n, qsfp_4_rx_n, qsfp_3_rx_n, qsfp_2_rx_n, qsfp_1_rx_n}),
.eth_gty_mgt_refclk_p({qsfp_9_mgt_refclk_p, qsfp_8_mgt_refclk_p, qsfp_7_mgt_refclk_p, qsfp_6_mgt_refclk_p, qsfp_5_mgt_refclk_p, qsfp_4_mgt_refclk_p, qsfp_3_mgt_refclk_p, qsfp_2_mgt_refclk_p, qsfp_1_mgt_refclk_p}),
.eth_gty_mgt_refclk_n({qsfp_9_mgt_refclk_n, qsfp_8_mgt_refclk_n, qsfp_7_mgt_refclk_n, qsfp_6_mgt_refclk_n, qsfp_5_mgt_refclk_n, qsfp_4_mgt_refclk_n, qsfp_3_mgt_refclk_n, qsfp_2_mgt_refclk_n, qsfp_1_mgt_refclk_n}),
.eth_gty_mgt_refclk_out(),
.eth_gty_tx_p(eth_gty_tx_p),
.eth_gty_tx_n(eth_gty_tx_n),
.eth_gty_rx_p(eth_gty_rx_p),
.eth_gty_rx_n(eth_gty_rx_n),
.eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p),
.eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n),
.eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out),
.eth_port_resetl({qsfp_9_resetl, qsfp_8_resetl, qsfp_7_resetl, qsfp_6_resetl, qsfp_5_resetl, qsfp_4_resetl, qsfp_3_resetl, qsfp_2_resetl, qsfp_1_resetl}),
.eth_port_modprsl({qsfp_9_modprsl, qsfp_8_modprsl, qsfp_7_modprsl, qsfp_6_modprsl, qsfp_5_modprsl, qsfp_4_modprsl, qsfp_3_modprsl, qsfp_2_modprsl, qsfp_1_modprsl}),

248
src/eth/example/HTG9200/fpga/rtl/fpga_6qsfp.sv
View File

@@ -66,90 +66,90 @@ module fpga #
/*
* Ethernet: QSFP28
*/
output wire logic [3:0] qsfp_1_tx_p,
output wire logic [3:0] qsfp_1_tx_n,
input wire logic [3:0] qsfp_1_rx_p,
input wire logic [3:0] qsfp_1_rx_n,
output wire logic qsfp_1_tx_p[4],
output wire logic qsfp_1_tx_n[4],
input wire logic qsfp_1_rx_p[4],
input wire logic qsfp_1_rx_n[4],
input wire logic qsfp_1_mgt_refclk_p,
input wire logic qsfp_1_mgt_refclk_n,
output wire logic qsfp_1_resetl,
input wire logic qsfp_1_modprsl,
input wire logic qsfp_1_intl,
output wire logic [3:0] qsfp_2_tx_p,
output wire logic [3:0] qsfp_2_tx_n,
input wire logic [3:0] qsfp_2_rx_p,
input wire logic [3:0] qsfp_2_rx_n,
output wire logic qsfp_2_tx_p[4],
output wire logic qsfp_2_tx_n[4],
input wire logic qsfp_2_rx_p[4],
input wire logic qsfp_2_rx_n[4],
input wire logic qsfp_2_mgt_refclk_p,
input wire logic qsfp_2_mgt_refclk_n,
output wire logic qsfp_2_resetl,
input wire logic qsfp_2_modprsl,
input wire logic qsfp_2_intl,
output wire logic [3:0] qsfp_3_tx_p,
output wire logic [3:0] qsfp_3_tx_n,
input wire logic [3:0] qsfp_3_rx_p,
input wire logic [3:0] qsfp_3_rx_n,
output wire logic qsfp_3_tx_p[4],
output wire logic qsfp_3_tx_n[4],
input wire logic qsfp_3_rx_p[4],
input wire logic qsfp_3_rx_n[4],
input wire logic qsfp_3_mgt_refclk_p,
input wire logic qsfp_3_mgt_refclk_n,
output wire logic qsfp_3_resetl,
input wire logic qsfp_3_modprsl,
input wire logic qsfp_3_intl,
output wire logic [3:0] qsfp_4_tx_p,
output wire logic [3:0] qsfp_4_tx_n,
input wire logic [3:0] qsfp_4_rx_p,
input wire logic [3:0] qsfp_4_rx_n,
output wire logic qsfp_4_tx_p[4],
output wire logic qsfp_4_tx_n[4],
input wire logic qsfp_4_rx_p[4],
input wire logic qsfp_4_rx_n[4],
input wire logic qsfp_4_mgt_refclk_p,
input wire logic qsfp_4_mgt_refclk_n,
output wire logic qsfp_4_resetl,
input wire logic qsfp_4_modprsl,
input wire logic qsfp_4_intl,
output wire logic [3:0] qsfp_5_tx_p,
output wire logic [3:0] qsfp_5_tx_n,
input wire logic [3:0] qsfp_5_rx_p,
input wire logic [3:0] qsfp_5_rx_n,
output wire logic qsfp_5_tx_p[4],
output wire logic qsfp_5_tx_n[4],
input wire logic qsfp_5_rx_p[4],
input wire logic qsfp_5_rx_n[4],
input wire logic qsfp_5_mgt_refclk_p,
input wire logic qsfp_5_mgt_refclk_n,
output wire logic qsfp_5_resetl,
input wire logic qsfp_5_modprsl,
input wire logic qsfp_5_intl,
output wire logic [3:0] qsfp_6_tx_p,
output wire logic [3:0] qsfp_6_tx_n,
input wire logic [3:0] qsfp_6_rx_p,
input wire logic [3:0] qsfp_6_rx_n,
output wire logic qsfp_6_tx_p[4],
output wire logic qsfp_6_tx_n[4],
input wire logic qsfp_6_rx_p[4],
input wire logic qsfp_6_rx_n[4],
input wire logic qsfp_6_mgt_refclk_p,
input wire logic qsfp_6_mgt_refclk_n,
output wire logic qsfp_6_resetl,
input wire logic qsfp_6_modprsl,
input wire logic qsfp_6_intl,
output wire logic [3:0] qsfp_7_tx_p,
output wire logic [3:0] qsfp_7_tx_n,
input wire logic [3:0] qsfp_7_rx_p,
input wire logic [3:0] qsfp_7_rx_n,
output wire logic qsfp_7_tx_p[4],
output wire logic qsfp_7_tx_n[4],
input wire logic qsfp_7_rx_p[4],
input wire logic qsfp_7_rx_n[4],
input wire logic qsfp_7_mgt_refclk_p,
input wire logic qsfp_7_mgt_refclk_n,
output wire logic qsfp_7_resetl,
input wire logic qsfp_7_modprsl,
input wire logic qsfp_7_intl,
output wire logic [3:0] qsfp_8_tx_p,
output wire logic [3:0] qsfp_8_tx_n,
input wire logic [3:0] qsfp_8_rx_p,
input wire logic [3:0] qsfp_8_rx_n,
output wire logic qsfp_8_tx_p[4],
output wire logic qsfp_8_tx_n[4],
input wire logic qsfp_8_rx_p[4],
input wire logic qsfp_8_rx_n[4],
input wire logic qsfp_8_mgt_refclk_p,
input wire logic qsfp_8_mgt_refclk_n,
output wire logic qsfp_8_resetl,
input wire logic qsfp_8_modprsl,
input wire logic qsfp_8_intl,
output wire logic [3:0] qsfp_9_tx_p,
output wire logic [3:0] qsfp_9_tx_n,
input wire logic [3:0] qsfp_9_rx_p,
input wire logic [3:0] qsfp_9_rx_n,
output wire logic qsfp_9_tx_p[4],
output wire logic qsfp_9_tx_n[4],
input wire logic qsfp_9_rx_p[4],
input wire logic qsfp_9_rx_n[4],
input wire logic qsfp_9_mgt_refclk_p,
input wire logic qsfp_9_mgt_refclk_n,
output wire logic qsfp_9_resetl,
@@ -159,10 +159,10 @@ module fpga #
/*
* Ethernet: QSFP28 via HTG 6x QSFP28 FMC+ adapter
*/
output wire logic [3:0] fmc_qsfp_1_tx_p,
output wire logic [3:0] fmc_qsfp_1_tx_n,
input wire logic [3:0] fmc_qsfp_1_rx_p,
input wire logic [3:0] fmc_qsfp_1_rx_n,
output wire logic fmc_qsfp_1_tx_p[4],
output wire logic fmc_qsfp_1_tx_n[4],
input wire logic fmc_qsfp_1_rx_p[4],
input wire logic fmc_qsfp_1_rx_n[4],
input wire logic fmc_qsfp_1_mgt_refclk_p,
input wire logic fmc_qsfp_1_mgt_refclk_n,
output wire logic fmc_qsfp_1_modsell,
@@ -171,10 +171,10 @@ module fpga #
input wire logic fmc_qsfp_1_intl,
output wire logic fmc_qsfp_1_lpmode,
output wire logic [3:0] fmc_qsfp_2_tx_p,
output wire logic [3:0] fmc_qsfp_2_tx_n,
input wire logic [3:0] fmc_qsfp_2_rx_p,
input wire logic [3:0] fmc_qsfp_2_rx_n,
output wire logic fmc_qsfp_2_tx_p[4],
output wire logic fmc_qsfp_2_tx_n[4],
input wire logic fmc_qsfp_2_rx_p[4],
input wire logic fmc_qsfp_2_rx_n[4],
input wire logic fmc_qsfp_2_mgt_refclk_p,
input wire logic fmc_qsfp_2_mgt_refclk_n,
output wire logic fmc_qsfp_2_modsell,
@@ -183,10 +183,10 @@ module fpga #
input wire logic fmc_qsfp_2_intl,
output wire logic fmc_qsfp_2_lpmode,
output wire logic [3:0] fmc_qsfp_3_tx_p,
output wire logic [3:0] fmc_qsfp_3_tx_n,
input wire logic [3:0] fmc_qsfp_3_rx_p,
input wire logic [3:0] fmc_qsfp_3_rx_n,
output wire logic fmc_qsfp_3_tx_p[4],
output wire logic fmc_qsfp_3_tx_n[4],
input wire logic fmc_qsfp_3_rx_p[4],
input wire logic fmc_qsfp_3_rx_n[4],
input wire logic fmc_qsfp_3_mgt_refclk_p,
input wire logic fmc_qsfp_3_mgt_refclk_n,
output wire logic fmc_qsfp_3_modsell,
@@ -195,10 +195,10 @@ module fpga #
input wire logic fmc_qsfp_3_intl,
output wire logic fmc_qsfp_3_lpmode,
output wire logic [3:0] fmc_qsfp_4_tx_p,
output wire logic [3:0] fmc_qsfp_4_tx_n,
input wire logic [3:0] fmc_qsfp_4_rx_p,
input wire logic [3:0] fmc_qsfp_4_rx_n,
output wire logic fmc_qsfp_4_tx_p[4],
output wire logic fmc_qsfp_4_tx_n[4],
input wire logic fmc_qsfp_4_rx_p[4],
input wire logic fmc_qsfp_4_rx_n[4],
input wire logic fmc_qsfp_4_mgt_refclk_p,
input wire logic fmc_qsfp_4_mgt_refclk_n,
output wire logic fmc_qsfp_4_modsell,
@@ -207,10 +207,10 @@ module fpga #
input wire logic fmc_qsfp_4_intl,
output wire logic fmc_qsfp_4_lpmode,
output wire logic [3:0] fmc_qsfp_5_tx_p,
output wire logic [3:0] fmc_qsfp_5_tx_n,
input wire logic [3:0] fmc_qsfp_5_rx_p,
input wire logic [3:0] fmc_qsfp_5_rx_n,
output wire logic fmc_qsfp_5_tx_p[4],
output wire logic fmc_qsfp_5_tx_n[4],
input wire logic fmc_qsfp_5_rx_p[4],
input wire logic fmc_qsfp_5_rx_n[4],
input wire logic fmc_qsfp_5_mgt_refclk_p,
input wire logic fmc_qsfp_5_mgt_refclk_n,
output wire logic fmc_qsfp_5_modsell,
@@ -219,10 +219,10 @@ module fpga #
input wire logic fmc_qsfp_5_intl,
output wire logic fmc_qsfp_5_lpmode,
output wire logic [3:0] fmc_qsfp_6_tx_p,
output wire logic [3:0] fmc_qsfp_6_tx_n,
input wire logic [3:0] fmc_qsfp_6_rx_p,
input wire logic [3:0] fmc_qsfp_6_rx_n,
output wire logic fmc_qsfp_6_tx_p[4],
output wire logic fmc_qsfp_6_tx_n[4],
input wire logic fmc_qsfp_6_rx_p[4],
input wire logic fmc_qsfp_6_rx_n[4],
input wire logic fmc_qsfp_6_mgt_refclk_p,
input wire logic fmc_qsfp_6_mgt_refclk_n,
output wire logic fmc_qsfp_6_modsell,
@@ -405,14 +405,20 @@ localparam GTY_QUAD_CNT = PORT_CNT;
localparam GTY_CNT = GTY_QUAD_CNT*4;
localparam GTY_CLK_CNT = GTY_QUAD_CNT;
wire eth_gty_tx_p[GTY_CNT];
wire eth_gty_tx_n[GTY_CNT];
wire eth_gty_rx_p[GTY_CNT];
wire eth_gty_rx_n[GTY_CNT];
wire eth_gty_mgt_refclk_p[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_n[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_out[GTY_CLK_CNT];
assign clk_gty2_fdec = 1'b0;
assign clk_gty2_finc = 1'b0;
assign clk_gty2_oe_n = 1'b0;
assign clk_gty2_sync_n = 1'b1;
assign clk_gty2_rst_n = !rst_125mhz_int;
wire [PORT_CNT-1:0] eth_gty_mgt_refclk_out;
// forward MGT ref clock to PLL on FMC+ board
OBUFDS obufds_fmc_refclk_inst (
.I(eth_gty_mgt_refclk_out[0]),
@@ -434,6 +440,112 @@ assign fmc_clk_rst_n = !rst_125mhz_int;
wire eth_pll_locked = clk_gty2_lol_n && fmc_clk_lol_n;
assign qsfp_1_tx_p = eth_gty_tx_p[4*0 +: 4];
assign qsfp_1_tx_n = eth_gty_tx_n[4*0 +: 4];
assign eth_gty_rx_p[4*0 +: 4] = qsfp_1_rx_p;
assign eth_gty_rx_n[4*0 +: 4] = qsfp_1_rx_n;
assign qsfp_2_tx_p = eth_gty_tx_p[4*1 +: 4];
assign qsfp_2_tx_n = eth_gty_tx_n[4*1 +: 4];
assign eth_gty_rx_p[4*1 +: 4] = qsfp_2_rx_p;
assign eth_gty_rx_n[4*1 +: 4] = qsfp_2_rx_n;
assign qsfp_3_tx_p = eth_gty_tx_p[4*2 +: 4];
assign qsfp_3_tx_n = eth_gty_tx_n[4*2 +: 4];
assign eth_gty_rx_p[4*2 +: 4] = qsfp_3_rx_p;
assign eth_gty_rx_n[4*2 +: 4] = qsfp_3_rx_n;
assign qsfp_4_tx_p = eth_gty_tx_p[4*3 +: 4];
assign qsfp_4_tx_n = eth_gty_tx_n[4*3 +: 4];
assign eth_gty_rx_p[4*3 +: 4] = qsfp_4_rx_p;
assign eth_gty_rx_n[4*3 +: 4] = qsfp_4_rx_n;
assign qsfp_5_tx_p = eth_gty_tx_p[4*4 +: 4];
assign qsfp_5_tx_n = eth_gty_tx_n[4*4 +: 4];
assign eth_gty_rx_p[4*4 +: 4] = qsfp_5_rx_p;
assign eth_gty_rx_n[4*4 +: 4] = qsfp_5_rx_n;
assign qsfp_6_tx_p = eth_gty_tx_p[4*5 +: 4];
assign qsfp_6_tx_n = eth_gty_tx_n[4*5 +: 4];
assign eth_gty_rx_p[4*5 +: 4] = qsfp_6_rx_p;
assign eth_gty_rx_n[4*5 +: 4] = qsfp_6_rx_n;
assign qsfp_7_tx_p = eth_gty_tx_p[4*6 +: 4];
assign qsfp_7_tx_n = eth_gty_tx_n[4*6 +: 4];
assign eth_gty_rx_p[4*6 +: 4] = qsfp_7_rx_p;
assign eth_gty_rx_n[4*6 +: 4] = qsfp_7_rx_n;
assign qsfp_8_tx_p = eth_gty_tx_p[4*7 +: 4];
assign qsfp_8_tx_n = eth_gty_tx_n[4*7 +: 4];
assign eth_gty_rx_p[4*7 +: 4] = qsfp_8_rx_p;
assign eth_gty_rx_n[4*7 +: 4] = qsfp_8_rx_n;
assign qsfp_9_tx_p = eth_gty_tx_p[4*8 +: 4];
assign qsfp_9_tx_n = eth_gty_tx_n[4*8 +: 4];
assign eth_gty_rx_p[4*8 +: 4] = qsfp_9_rx_p;
assign eth_gty_rx_n[4*8 +: 4] = qsfp_9_rx_n;
assign fmc_qsfp_1_tx_p = eth_gty_tx_p[4*9 +: 4];
assign fmc_qsfp_1_tx_n = eth_gty_tx_n[4*9 +: 4];
assign eth_gty_rx_p[4*9 +: 4] = fmc_qsfp_1_rx_p;
assign eth_gty_rx_n[4*9 +: 4] = fmc_qsfp_1_rx_n;
assign fmc_qsfp_2_tx_p = eth_gty_tx_p[4*10 +: 4];
assign fmc_qsfp_2_tx_n = eth_gty_tx_n[4*10 +: 4];
assign eth_gty_rx_p[4*10 +: 4] = fmc_qsfp_2_rx_p;
assign eth_gty_rx_n[4*10 +: 4] = fmc_qsfp_2_rx_n;
assign fmc_qsfp_3_tx_p = eth_gty_tx_p[4*11 +: 4];
assign fmc_qsfp_3_tx_n = eth_gty_tx_n[4*11 +: 4];
assign eth_gty_rx_p[4*11 +: 4] = fmc_qsfp_3_rx_p;
assign eth_gty_rx_n[4*11 +: 4] = fmc_qsfp_3_rx_n;
assign fmc_qsfp_4_tx_p = eth_gty_tx_p[4*12 +: 4];
assign fmc_qsfp_4_tx_n = eth_gty_tx_n[4*12 +: 4];
assign eth_gty_rx_p[4*12 +: 4] = fmc_qsfp_4_rx_p;
assign eth_gty_rx_n[4*12 +: 4] = fmc_qsfp_4_rx_n;
assign fmc_qsfp_5_tx_p = eth_gty_tx_p[4*13 +: 4];
assign fmc_qsfp_5_tx_n = eth_gty_tx_n[4*13 +: 4];
assign eth_gty_rx_p[4*13 +: 4] = fmc_qsfp_5_rx_p;
assign eth_gty_rx_n[4*13 +: 4] = fmc_qsfp_5_rx_n;
assign fmc_qsfp_6_tx_p = eth_gty_tx_p[4*14 +: 4];
assign fmc_qsfp_6_tx_n = eth_gty_tx_n[4*14 +: 4];
assign eth_gty_rx_p[4*14 +: 4] = fmc_qsfp_6_rx_p;
assign eth_gty_rx_n[4*14 +: 4] = fmc_qsfp_6_rx_n;
assign eth_gty_mgt_refclk_p[0] = qsfp_1_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[0] = qsfp_1_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[1] = qsfp_2_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[1] = qsfp_2_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[2] = qsfp_3_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[2] = qsfp_3_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[3] = qsfp_4_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[3] = qsfp_4_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[4] = qsfp_5_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[4] = qsfp_5_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[5] = qsfp_6_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[5] = qsfp_6_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[6] = qsfp_7_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[6] = qsfp_7_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[7] = qsfp_8_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[7] = qsfp_8_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[8] = qsfp_9_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[8] = qsfp_9_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[9] = fmc_qsfp_1_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[9] = fmc_qsfp_1_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[10] = fmc_qsfp_2_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[10] = fmc_qsfp_2_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[11] = fmc_qsfp_3_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[11] = fmc_qsfp_3_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[12] = fmc_qsfp_4_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[12] = fmc_qsfp_4_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[13] = fmc_qsfp_5_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[13] = fmc_qsfp_5_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[14] = fmc_qsfp_6_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[14] = fmc_qsfp_6_mgt_refclk_n;
fpga_core #(
.SIM(SIM),
.VENDOR(VENDOR),
@@ -481,12 +593,12 @@ core_inst (
*/
.eth_pll_locked(eth_pll_locked),
.eth_gty_tx_p({fmc_qsfp_6_tx_p, fmc_qsfp_5_tx_p, fmc_qsfp_4_tx_p, fmc_qsfp_3_tx_p, fmc_qsfp_2_tx_p, fmc_qsfp_1_tx_p, qsfp_9_tx_p, qsfp_8_tx_p, qsfp_7_tx_p, qsfp_6_tx_p, qsfp_5_tx_p, qsfp_4_tx_p, qsfp_3_tx_p, qsfp_2_tx_p, qsfp_1_tx_p}),
.eth_gty_tx_n({fmc_qsfp_6_tx_n, fmc_qsfp_5_tx_n, fmc_qsfp_4_tx_n, fmc_qsfp_3_tx_n, fmc_qsfp_2_tx_n, fmc_qsfp_1_tx_n, qsfp_9_tx_n, qsfp_8_tx_n, qsfp_7_tx_n, qsfp_6_tx_n, qsfp_5_tx_n, qsfp_4_tx_n, qsfp_3_tx_n, qsfp_2_tx_n, qsfp_1_tx_n}),
.eth_gty_rx_p({fmc_qsfp_6_rx_p, fmc_qsfp_5_rx_p, fmc_qsfp_4_rx_p, fmc_qsfp_3_rx_p, fmc_qsfp_2_rx_p, fmc_qsfp_1_rx_p, qsfp_9_rx_p, qsfp_8_rx_p, qsfp_7_rx_p, qsfp_6_rx_p, qsfp_5_rx_p, qsfp_4_rx_p, qsfp_3_rx_p, qsfp_2_rx_p, qsfp_1_rx_p}),
.eth_gty_rx_n({fmc_qsfp_6_rx_n, fmc_qsfp_5_rx_n, fmc_qsfp_4_rx_n, fmc_qsfp_3_rx_n, fmc_qsfp_2_rx_n, fmc_qsfp_1_rx_n, qsfp_9_rx_n, qsfp_8_rx_n, qsfp_7_rx_n, qsfp_6_rx_n, qsfp_5_rx_n, qsfp_4_rx_n, qsfp_3_rx_n, qsfp_2_rx_n, qsfp_1_rx_n}),
.eth_gty_mgt_refclk_p({fmc_qsfp_6_mgt_refclk_p, fmc_qsfp_5_mgt_refclk_p, fmc_qsfp_4_mgt_refclk_p, fmc_qsfp_3_mgt_refclk_p, fmc_qsfp_2_mgt_refclk_p, fmc_qsfp_1_mgt_refclk_p, qsfp_9_mgt_refclk_p, qsfp_8_mgt_refclk_p, qsfp_7_mgt_refclk_p, qsfp_6_mgt_refclk_p, qsfp_5_mgt_refclk_p, qsfp_4_mgt_refclk_p, qsfp_3_mgt_refclk_p, qsfp_2_mgt_refclk_p, qsfp_1_mgt_refclk_p}),
.eth_gty_mgt_refclk_n({fmc_qsfp_6_mgt_refclk_n, fmc_qsfp_5_mgt_refclk_n, fmc_qsfp_4_mgt_refclk_n, fmc_qsfp_3_mgt_refclk_n, fmc_qsfp_2_mgt_refclk_n, fmc_qsfp_1_mgt_refclk_n, qsfp_9_mgt_refclk_n, qsfp_8_mgt_refclk_n, qsfp_7_mgt_refclk_n, qsfp_6_mgt_refclk_n, qsfp_5_mgt_refclk_n, qsfp_4_mgt_refclk_n, qsfp_3_mgt_refclk_n, qsfp_2_mgt_refclk_n, qsfp_1_mgt_refclk_n}),
.eth_gty_tx_p(eth_gty_tx_p),
.eth_gty_tx_n(eth_gty_tx_n),
.eth_gty_rx_p(eth_gty_rx_p),
.eth_gty_rx_n(eth_gty_rx_n),
.eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p),
.eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n),
.eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out),
.eth_port_resetl({fmc_qsfp_6_resetl, fmc_qsfp_5_resetl, fmc_qsfp_4_resetl, fmc_qsfp_3_resetl, fmc_qsfp_2_resetl, fmc_qsfp_1_resetl, qsfp_9_resetl, qsfp_8_resetl, qsfp_7_resetl, qsfp_6_resetl, qsfp_5_resetl, qsfp_4_resetl, qsfp_3_resetl, qsfp_2_resetl, qsfp_1_resetl}),

86
src/eth/example/HTG9200/fpga/rtl/fpga_core.sv
View File

@@ -63,13 +63,13 @@ module fpga_core #
*/
input wire logic eth_pll_locked,
output wire logic [GTY_CNT-1:0] eth_gty_tx_p,
output wire logic [GTY_CNT-1:0] eth_gty_tx_n,
input wire logic [GTY_CNT-1:0] eth_gty_rx_p,
input wire logic [GTY_CNT-1:0] eth_gty_rx_n,
input wire logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_p,
input wire logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_n,
output wire logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_out,
output wire logic eth_gty_tx_p[GTY_CNT],
output wire logic eth_gty_tx_n[GTY_CNT],
input wire logic eth_gty_rx_p[GTY_CNT],
input wire logic eth_gty_rx_n[GTY_CNT],
input wire logic eth_gty_mgt_refclk_p[GTY_CLK_CNT],
input wire logic eth_gty_mgt_refclk_n[GTY_CLK_CNT],
output wire logic eth_gty_mgt_refclk_out[GTY_CLK_CNT],
output wire logic [PORT_CNT-1:0] eth_port_resetl,
input wire logic [PORT_CNT-1:0] eth_port_modprsl,
@@ -289,23 +289,23 @@ xfcp_mod_i2c_inst (
wire eth_reset = SIM ? 1'b0 : (si5341_i2c_busy || !eth_pll_locked);
assign eth_port_resetl = {PORT_CNT{~eth_reset}};
wire [GTY_CNT-1:0] eth_gty_tx_clk;
wire [GTY_CNT-1:0] eth_gty_tx_rst;
wire eth_gty_tx_clk[GTY_CNT];
wire eth_gty_tx_rst[GTY_CNT];
taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_tx[GTY_CNT]();
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) eth_gty_axis_tx_cpl[GTY_CNT]();
wire [GTY_CNT-1:0] eth_gty_rx_clk;
wire [GTY_CNT-1:0] eth_gty_rx_rst;
wire eth_gty_rx_clk[GTY_CNT];
wire eth_gty_rx_rst[GTY_CNT];
taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_rx[GTY_CNT]();
wire [GTY_CNT-1:0] eth_gty_rx_status;
wire eth_gty_rx_status[GTY_CNT];
wire [GTY_QUAD_CNT-1:0] eth_gty_gtpowergood;
wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk;
wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_bufg;
wire eth_gty_mgt_refclk[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_bufg[GTY_CLK_CNT];
wire [GTY_CLK_CNT-1:0] eth_gty_rst;
wire eth_gty_rst[GTY_CLK_CNT];
for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk
@@ -456,12 +456,12 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
* MAC clocks
*/
.rx_clk(eth_gty_rx_clk[n*CNT +: CNT]),
.rx_rst_in('0),
.rx_rst_in('{CNT{1'b0}}),
.rx_rst_out(eth_gty_rx_rst[n*CNT +: CNT]),
.tx_clk(eth_gty_tx_clk[n*CNT +: CNT]),
.tx_rst_in('0),
.tx_rst_in('{CNT{1'b0}}),
.tx_rst_out(eth_gty_tx_rst[n*CNT +: CNT]),
.ptp_sample_clk('0),
.ptp_sample_clk('{CNT{1'b0}}),
/*
* Transmit interface (AXI stream)
@@ -478,24 +478,24 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
* PTP clock
*/
.tx_ptp_ts('{CNT{'0}}),
.tx_ptp_ts_step('0),
.tx_ptp_ts_step('{CNT{1'b0}}),
.rx_ptp_ts('{CNT{'0}}),
.rx_ptp_ts_step('0),
.rx_ptp_ts_step('{CNT{1'b0}}),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
.tx_lfc_req('0),
.tx_lfc_resend('0),
.rx_lfc_en('0),
.tx_lfc_req('{CNT{1'b0}}),
.tx_lfc_resend('{CNT{1'b0}}),
.rx_lfc_en('{CNT{1'b0}}),
.rx_lfc_req(),
.rx_lfc_ack('0),
.rx_lfc_ack('{CNT{1'b0}}),
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('{CNT{'0}}),
.tx_pfc_resend('0),
.tx_pfc_resend('{CNT{1'b0}}),
.rx_pfc_en('{CNT{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('{CNT{'0}}),
@@ -503,8 +503,8 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
/*
* Pause interface
*/
.tx_lfc_pause_en('0),
.tx_pause_req('0),
.tx_lfc_pause_en('{CNT{1'b0}}),
.tx_pause_req('{CNT{1'b0}}),
.tx_pause_ack(),
/*
@@ -549,7 +549,7 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
.stat_rx_err_bad_block(),
.stat_rx_err_framing(),
.stat_rx_err_preamble(),
.stat_rx_fifo_drop('0),
.stat_rx_fifo_drop('{CNT{1'b0}}),
.stat_tx_mcf(),
.stat_rx_mcf(),
.stat_tx_lfc_pkt(),
@@ -574,42 +574,42 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
*/
.cfg_tx_max_pkt_len('{CNT{16'd9218}}),
.cfg_tx_ifg('{CNT{8'd12}}),
.cfg_tx_enable('1),
.cfg_tx_enable('{CNT{1'b1}}),
.cfg_rx_max_pkt_len('{CNT{16'd9218}}),
.cfg_rx_enable('1),
.cfg_tx_prbs31_enable('0),
.cfg_rx_prbs31_enable('0),
.cfg_rx_enable('{CNT{1'b1}}),
.cfg_tx_prbs31_enable('{CNT{1'b0}}),
.cfg_rx_prbs31_enable('{CNT{1'b0}}),
.cfg_mcf_rx_eth_dst_mcast('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_mcf_rx_check_eth_dst_mcast('1),
.cfg_mcf_rx_check_eth_dst_mcast('{CNT{1'b1}}),
.cfg_mcf_rx_eth_dst_ucast('{CNT{48'd0}}),
.cfg_mcf_rx_check_eth_dst_ucast('0),
.cfg_mcf_rx_check_eth_dst_ucast('{CNT{1'b0}}),
.cfg_mcf_rx_eth_src('{CNT{48'd0}}),
.cfg_mcf_rx_check_eth_src('0),
.cfg_mcf_rx_check_eth_src('{CNT{1'b0}}),
.cfg_mcf_rx_eth_type('{CNT{16'h8808}}),
.cfg_mcf_rx_opcode_lfc('{CNT{16'h0001}}),
.cfg_mcf_rx_check_opcode_lfc('1),
.cfg_mcf_rx_check_opcode_lfc('{CNT{1'b1}}),
.cfg_mcf_rx_opcode_pfc('{CNT{16'h0101}}),
.cfg_mcf_rx_check_opcode_pfc('1),
.cfg_mcf_rx_forward('0),
.cfg_mcf_rx_enable('0),
.cfg_mcf_rx_check_opcode_pfc('{CNT{1'b1}}),
.cfg_mcf_rx_forward('{CNT{1'b0}}),
.cfg_mcf_rx_enable('{CNT{1'b0}}),
.cfg_tx_lfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_tx_lfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
.cfg_tx_lfc_eth_type('{CNT{16'h8808}}),
.cfg_tx_lfc_opcode('{CNT{16'h0001}}),
.cfg_tx_lfc_en('0),
.cfg_tx_lfc_en('{CNT{1'b0}}),
.cfg_tx_lfc_quanta('{CNT{16'hffff}}),
.cfg_tx_lfc_refresh('{CNT{16'h7fff}}),
.cfg_tx_pfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_tx_pfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
.cfg_tx_pfc_eth_type('{CNT{16'h8808}}),
.cfg_tx_pfc_opcode('{CNT{16'h0101}}),
.cfg_tx_pfc_en('0),
.cfg_tx_pfc_en('{CNT{1'b0}}),
.cfg_tx_pfc_quanta('{CNT{'{8{16'hffff}}}}),
.cfg_tx_pfc_refresh('{CNT{'{8{16'h7fff}}}}),
.cfg_rx_lfc_opcode('{CNT{16'h0001}}),
.cfg_rx_lfc_en('0),
.cfg_rx_lfc_en('{CNT{1'b0}}),
.cfg_rx_pfc_opcode('{CNT{16'h0101}}),
.cfg_rx_pfc_en('0)
.cfg_rx_pfc_en('{CNT{1'b0}})
);
end

14
src/eth/example/HTG9200/fpga/tb/fpga_core/test_fpga_core.py
View File

@@ -49,6 +49,9 @@ class TB:
self.qsfp_sources = []
self.qsfp_sinks = []
for clk in dut.eth_gty_mgt_refclk_p:
cocotb.start_soon(Clock(clk, 6.206, units="ns").start())
for inst in dut.gty_quad:
for ch in inst.mac_inst.ch:
gt_inst = ch.ch_inst.gt.gt_inst
@@ -91,8 +94,6 @@ class TB:
dut.eth_port_modprsl.setimmediatevalue(0)
dut.eth_port_intl.setimmediatevalue(0)
cocotb.start_soon(self._run_refclk())
async def init(self):
self.dut.rst_125mhz.setimmediatevalue(0)
@@ -110,15 +111,6 @@ class TB:
for k in range(10):
await RisingEdge(self.dut.clk_125mhz)
async def _run_refclk(self):
t = Timer(3.102, 'ns')
val = 2**len(self.dut.eth_gty_mgt_refclk_p)-1
while True:
self.dut.eth_gty_mgt_refclk_p.value = val
await t
self.dut.eth_gty_mgt_refclk_p.value = 0
await t
async def mac_test(tb, source, sink):
tb.log.info("Test MAC")