Add efinix ddio primitives

src/io/rtl/taxi_iddr.sv

@@ -19,7 +19,7 @@ module taxi_iddr #
 (
     // simulation (set to avoid vendor primitives)
     parameter logic SIM = 1'b0,
-    // vendor ("GENERIC", "XILINX", "ALTERA")
+    // vendor ("GENERIC", "XILINX", "ALTERA", "EFINIX")
     parameter string VENDOR = "XILINX",
     // device family
     parameter string FAMILY = "virtex7",
@@ -125,6 +125,45 @@ end else if (!SIM && VENDOR == "ALTERA") begin
 
     assign q1 = q1_delay;
 
+end else if (!SIM && VENDOR == "EFINIX") begin
+    // Titanium (and Topaz) supports pipeline mode, Trion does not
+    if (FAMILY == "titanium") begin
+        for (genvar n = 0; n < WIDTH; n = n + 1) begin : iddr
+            EFX_IDDIO #(
+                .PULL_OPTION("NONE"),
+                .IS_CLK_INVERTED(0),
+                .MODE("DDIO_PIPE")
+            ) efx_iddio_inst (
+                .O_HI(q1[n]),
+                .O_LO(q2[n]),
+                .I(d[n]),
+                .CLK(clk)
+            );
+        end
+    end else begin
+        for (genvar n = 0; n < WIDTH; n = n + 1) begin : iddr
+            wire q1_int;
+            reg q1_delay;
+
+            EFX_IDDIO #(
+                .PULL_OPTION("NONE"),
+                .IS_CLK_INVERTED(0),
+                .MODE("DDIO_RESYNC")
+            ) efx_iddio_inst (
+                .O_HI(q1_int),
+                .O_LO(q2[n]),
+                .I(d[n]),
+                .CLK(clk)
+            );
+
+            always @(posedge clk) begin
+                q1_delay <= q1_int;
+            end
+
+            assign q1[n] = q1_delay;
+        end
+    end
+
 end else begin
     // generic/simulation implementation (no vendor primitives)
 

src/io/rtl/taxi_oddr.sv

@@ -109,6 +109,19 @@ end else if (!SIM && VENDOR == "ALTERA") begin
         .dataout(q)
     );
 
+end else if (VENDOR == "EFINIX") begin
+    for (genvar n = 0; n < WIDTH; n = n + 1) begin : IDDIO_LOOP
+        EFX_ODDIO #(
+            .IS_CLK_INVERTED(0),
+            .MODE("DDIO_RESYNC")
+        ) u_oddio (
+            .I_HI(d1[n]),
+            .I_LO(d2[n]),
+            .O(q[n]),
+            .CLK(clk)
+        );
+    end
+
 end else begin
     // generic/simulation implementation (no vendor primitives)