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• 665599d748 example/ZCU102: Add XFCP to ZCU102 example design for monitoring and control Alex Forencich 2025-04-09 19:22:16 -07:00
• 28fd0f8cba example/Arty: Arty example design clean-up Alex Forencich 2025-04-09 19:12:57 -07:00
• d355956b68 example/KCU105: Add XFCP to KCU105 example design for monitoring and control Alex Forencich 2025-04-09 19:11:54 -07:00
• 50e5dca188 example/VCU108: Add XFCP to VCU108 example design for monitoring and control Alex Forencich 2025-04-09 18:58:44 -07:00
• f2b5ea5c0b example/HTG940: Add XFCP to HTG940 example design for monitoring and control Alex Forencich 2025-04-09 18:45:55 -07:00
• 7895a01c4f example/VCU108: Fix MMCM config on VCU108 Alex Forencich 2025-04-09 18:43:02 -07:00
• 71a1952dd8 example/KC705: Add XFCP to KC705 example design for monitoring and control Alex Forencich 2025-04-09 17:53:13 -07:00
• e799e4e488 example/ZCU106: Add XFCP to ZCU106 example design for monitoring and control Alex Forencich 2025-04-09 17:43:29 -07:00
• 62ccbcd22c example/KC705: Fix UART IOSTANDARD for KC705 Alex Forencich 2025-04-09 17:21:49 -07:00
• fee23c0bf8 example/VCU118: Add XFCP to VCU118 example design for monitoring and control Alex Forencich 2025-04-09 16:05:27 -07:00
• a5b7b8031b example/Alveo: Add XFCP to Alveo example design for monitoring and control Alex Forencich 2025-04-09 16:05:10 -07:00
• ecfb50641d axis: Fix async FIFO timing constraints when using distributed RAM Alex Forencich 2025-04-09 14:24:12 -07:00
• 04718790ae example: Update 10G MAC instances in example designs Alex Forencich 2025-04-09 13:01:47 -07:00
• 93d9c8c9f6 eth: Add MAC statistics module to 10G MAC+PCS Alex Forencich 2025-04-09 12:18:42 -07:00
• ddf1b37f4e example/Arty: Add XFCP to Arty example design for monitoring and control Alex Forencich 2025-04-09 12:17:46 -07:00
• abadd72b1d stats: Fix naming in statistics counter module Alex Forencich 2025-04-09 10:05:41 -07:00
• 2714583a57 xfcp: Add XFCP statistics counter module Alex Forencich 2025-04-09 00:22:18 -07:00
• 06e9588609 axis: Fix parameter accesses in interface arrays Alex Forencich 2025-04-09 00:08:16 -07:00
• c4304bf8c0 example: Update 1G MAC instances in example designs Alex Forencich 2025-04-08 22:12:52 -07:00
• e90340db6e eth: Add MAC statistics module to 1G MACs Alex Forencich 2025-04-08 20:22:53 -07:00
• bb90cd5a08 eth: Add MAC statistics module to 10G MAC Alex Forencich 2025-04-08 20:18:43 -07:00
• 3106fd5a96 eth: Add MAC statistics module Alex Forencich 2025-04-08 10:49:45 -07:00
• f920e56348 eth: Add frame length enforcement and additional statistics outputs to taxi_axis_baser_rx_64 Alex Forencich 2025-04-07 23:37:29 -07:00
• c69eb63a69 eth: Add frame length enforcement and additional statistics outputs to taxi_axis_xgmii_rx_64 Alex Forencich 2025-04-07 23:29:50 -07:00
• a53d18b9d3 eth: Add frame length enforcement and additional statistics outputs to taxi_axis_xgmii_rx_32 Alex Forencich 2025-04-07 23:28:59 -07:00
• cb148ee905 eth: Report PHY-signalled errors as framing errors instead of bad blocks Alex Forencich 2025-04-07 23:02:23 -07:00
• f8890e4d80 eth: Add frame length enforcement and additional statistics outputs to taxi_axis_baser_tx_64 Alex Forencich 2025-04-07 22:03:26 -07:00
• 4fd3028f77 eth: Add frame length enforcement and additional statistics outputs to taxi_axis_xgmii_tx_64 Alex Forencich 2025-04-07 22:01:57 -07:00
• 6d31116596 eth: Add frame length enforcement and additional statistics outputs to taxi_axis_xgmii_tx_32 Alex Forencich 2025-04-07 22:00:34 -07:00
• 07e781e186 eth: Improve oversize frame tests Alex Forencich 2025-04-07 17:21:36 -07:00
• 1b28dc4b9a eth: Check stats outputs in AXI stream GMII RX module testbench Alex Forencich 2025-04-07 13:32:03 -07:00
• 2e05b1eff2 eth: Fix RX byte statistics strobe on AXIS GMII RX module Alex Forencich 2025-04-07 13:31:50 -07:00
• b073fc8efb eth: Check stats outputs in AXI stream GMII TX module testbench Alex Forencich 2025-04-07 13:25:53 -07:00
• bc023296f4 eth: Do not count SFD as payload data Alex Forencich 2025-04-07 13:25:39 -07:00
• 0ef0bb3409 eth: Add frame length enforcement and additional statistics outputs to taxi_axis_gmii_rx Alex Forencich 2025-04-06 00:17:31 -07:00
• 5582eddfa8 eth: Add frame length enforcement and additional statistics outputs to taxi_axis_gmii_tx Alex Forencich 2025-04-05 22:15:39 -07:00
• 4f45ac950d example/ZCU106: Add FMC pins Alex Forencich 2025-03-30 17:57:02 -07:00
• 04c62961aa example/ZCU102: Add FMC pins Alex Forencich 2025-03-30 17:56:53 -07:00
• 7a53e8f33c example/ZCU106: Clean up BASE-X core instances Alex Forencich 2025-03-30 17:55:59 -07:00
• 0a2e6dd573 example/ZCU102: Clean up BASE-X core instances Alex Forencich 2025-03-30 17:55:43 -07:00
• a56939313a example/ZCU102: Fix IOSTANDARD settings for UART pins Alex Forencich 2025-03-30 16:46:47 -07:00
• df87998a1b eth: Clean up error detection logic in combined MAC/PCS Alex Forencich 2025-03-27 09:33:56 -07:00
• 5b16933210 eth: Test more lengths to shift alignment Alex Forencich 2025-03-26 23:13:13 -07:00
• bec324dc03 eth: Fix bugs in 10G MAC RX related to short IFGs Alex Forencich 2025-03-26 23:03:57 -07:00
• 75a3909c37 eth: Add default IFG setting to Ethernet MAC TX modules Alex Forencich 2025-03-26 20:13:47 -07:00
• b0bdf8ee17 Update readme Alex Forencich 2025-03-26 00:13:12 -07:00
• c4fe84c9ff Update readthedocs config Alex Forencich 2025-03-25 23:58:46 -07:00
• 8ecb68ae01 Update readme Alex Forencich 2025-03-25 00:04:54 -07:00
• 4f830c8a12 axi: Remove extraneous interface declarations Alex Forencich 2025-03-25 00:03:42 -07:00
• d2b0fa4693 stats: Add statistics counter module and testbench Alex Forencich 2025-03-25 00:02:58 -07:00
• fd3e23ef6e stats: Add statistics collector module and testbench Alex Forencich 2025-03-24 23:22:04 -07:00
• ee4d0da13e example/VCU118: Clarify MDIO prescaler setting Alex Forencich 2025-03-24 00:04:36 -07:00
• c7cf9cc1bf example: Clean up and annotate USB UART connections Alex Forencich 2025-03-20 17:32:31 -07:00
• 315a4715ff xfcp: Fix localparam definition Alex Forencich 2025-03-19 16:32:17 -07:00
• 2fd346269f xfcp: Add XFCP I2C master module Alex Forencich 2025-03-19 15:56:39 -07:00
• b8021192e3 lss: Clean up I2C testbenches Alex Forencich 2025-03-19 14:52:26 -07:00
• 79e0bf6976 lss: Remove redundant tristate control outputs on I2C modules Alex Forencich 2025-03-19 12:41:39 -07:00
• fa2385aedb lss: Add I2C single register module and testbench Alex Forencich 2025-03-19 12:15:47 -07:00
• 44c811f82a lss: Add I2C master module and testbench Alex Forencich 2025-03-19 10:41:16 -07:00
• 1e3e298d9e Add cocotbext-i2c to tox.ini Alex Forencich 2025-03-19 10:18:03 -07:00
• a86f858116 docs: Add readthedocs yaml file Alex Forencich 2025-03-18 16:23:30 -07:00
• 115bacae02 docs: Add sphinx infrastructure Alex Forencich 2025-03-18 16:12:49 -07:00
• 3624976f0e hip: Add support for optional phase shifter clock to fractional MMCM module Alex Forencich 2025-03-17 21:05:49 -07:00
• d7e29a2b5c hip: Add support for optional cascaded MMCM for offset clock Alex Forencich 2025-03-17 21:04:52 -07:00
• b468d92e39 hip: Report error if fractional MMCM configuration does not work Alex Forencich 2025-03-17 21:00:12 -07:00
• eacae099bf hip: Add fractional MMCM wrapper for generating offset clocks for DDMTD Alex Forencich 2025-03-13 21:00:09 -07:00
• ebeadee172 lss: Implement fractional baud rate generation for UART Alex Forencich 2025-03-11 23:49:39 -07:00
• 1c686391ab lss: Refactor UART module to split out and share baud rate generation logic Alex Forencich 2025-03-11 23:09:19 -07:00
• 7df14e54e5 xfcp: Rename signals based on upstream/downstsream port role and data direction to simplify connections Alex Forencich 2025-03-11 18:33:57 -07:00
• 8d4ad59727 Update readme Alex Forencich 2025-03-10 17:04:03 -07:00
• 15653923fd xfcp: Add XFCP switch module and testbench Alex Forencich 2025-03-10 15:30:59 -07:00
• 0ee729b744 xfcp: Add XFCP AXI module and testbench Alex Forencich 2025-03-10 13:28:05 -07:00
• 70d77c8a95 xfcp: Add XFCP AXI lite module and testbench Alex Forencich 2025-03-10 13:25:55 -07:00
• ed9e8ffab3 eth: Use unpacked arrays for multidimensional ports Alex Forencich 2025-03-07 11:05:58 -08:00
• 6e4988f010 eth: Fix PFC/LFC tests for 10G MAC+PHY Alex Forencich 2025-03-07 10:41:49 -08:00
• cb04b84e18 example/VCU118: Add example design for VCU118 Alex Forencich 2025-03-07 00:29:17 -08:00
• 024353c68a lss: Add MDIO master Alex Forencich 2025-03-06 23:48:57 -08:00
• ed325acb1e axis: Implement tstrb in pipeline FIFO Alex Forencich 2025-03-06 16:18:20 -08:00
• e9ac4947ba axis: Normalize unpacked dimension Alex Forencich 2025-03-06 16:17:05 -08:00
• 56215865da axi: Normalize unpacked dimension Alex Forencich 2025-03-06 16:16:29 -08:00
• c422297666 axis: Tie off unused sideband signals in COBS encoder Alex Forencich 2025-03-06 16:11:38 -08:00
• 194a686bda xfcp: Add XFCP UART interface module and testbench Alex Forencich 2025-03-04 22:05:11 -08:00
• 98ea651532 axis: Use unpacked arrays for unpacking interface signals Alex Forencich 2025-02-28 23:24:56 -08:00
• 56a3c9f1ba axis: Add AXI stream arbitrated multiplexer module and testbench Alex Forencich 2025-02-28 23:24:40 -08:00
• 46e60d32f2 prim: Add arbiter module and testbench Alex Forencich 2025-02-28 21:04:49 -08:00
• 5966d05740 prim: Add priority encoder and testbench Alex Forencich 2025-02-28 21:04:32 -08:00
• a790e270b8 axi: Replace reg with logic in AXI lite RAM Alex Forencich 2025-02-27 13:44:18 -08:00
• df300b7dad axis: Add AXI stream multiplexer module and testbench Alex Forencich 2025-02-27 13:28:02 -08:00
• aa9900de94 axi: Add STRB parameters to testbenches Alex Forencich 2025-02-27 10:06:56 -08:00
• ff2e3c1331 Update readme Alex Forencich 2025-02-27 00:59:30 -08:00
• ad3042e090 axi: Add AXI lite dual-port RAM module and testbench Alex Forencich 2025-02-27 00:58:30 -08:00
• 55c097f47d axi: Add AXI RAM module and testbench Alex Forencich 2025-02-27 00:27:11 -08:00
• 0632b1982e axi: Add AXI lite RAM module and testbench Alex Forencich 2025-02-27 00:26:03 -08:00
• c478f187b1 Update readme Alex Forencich 2025-02-26 21:09:29 -08:00
• ae26b61200 axi: Add AXI register module and testbench Alex Forencich 2025-02-26 21:08:39 -08:00
• 1075896ecc axi: Add AXI lite register module and testbench Alex Forencich 2025-02-26 21:02:50 -08:00
• 5e5bce9aa0 axi: Add SV interface for AXI Alex Forencich 2025-02-26 20:51:25 -08:00
• 5f9f71e615 axi: Add SV interface for AXI lite Alex Forencich 2025-02-26 20:51:16 -08:00
• f419b3167a axis: Switch AXI stream interface license to MIT Alex Forencich 2025-02-26 20:50:40 -08:00
• da3996cf5c example/ADM_PCIE_9V3: Example design cleanup Alex Forencich 2025-02-26 14:16:18 -08:00