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  • da3996cf5c example/ADM_PCIE_9V3: Example design cleanup Alex Forencich 2025-02-26 14:16:18 -08:00
  • c6cbb57fe7 lss: Extract UART data width setting from interface Alex Forencich 2025-02-26 14:15:42 -08:00
  • 07d75f231a eth: Fix testbenches Alex Forencich 2025-02-25 17:35:09 -08:00
  • 01f836a2f9 example/KR260: Remove drive strength settings from input pins Alex Forencich 2025-02-25 17:18:08 -08:00
  • cf44abae0d axis: Use signal sync module for async FIFO output pause Alex Forencich 2025-02-25 17:13:10 -08:00
  • 181691941f eth: Use signal sync module for RGMII MAC speed detection Alex Forencich 2025-02-25 17:12:50 -08:00
  • f8d5d6a45e eth: Use signal sync module for GMII MAC speed detection Alex Forencich 2025-02-25 17:12:10 -08:00
  • 64c1cb1e39 eth: Use signal sync module for internal MAC pause handling Alex Forencich 2025-02-25 16:27:37 -08:00
  • 84fb93b5c3 example: Add signal sync timing constraints to example designs Alex Forencich 2025-02-25 16:04:32 -08:00
  • 8785c1517b example/fb2CG: Add example design for fb2CG@KU15P Alex Forencich 2025-02-25 15:49:21 -08:00
  • 5a8ac23922 io: Add LED shift register driver module Alex Forencich 2025-02-25 15:44:57 -08:00
  • 6e90f4f0a0 syn: Add timing constraints for signal synchronizer Alex Forencich 2025-02-25 15:39:00 -08:00
  • eae85cb8c7 syn: Clean up timing constraints for reset sync Alex Forencich 2025-02-25 15:38:39 -08:00
  • d0c7d7735a example/Nexus_K3P_Q: Reorganize MAC instances Alex Forencich 2025-02-25 12:20:01 -08:00
  • abb0ca1bcc example/ADM_PCIE_9V3: Reorganize MAC instances Alex Forencich 2025-02-25 12:01:20 -08:00
  • b18b643eed example/Alveo: Add example design for Xilinx Alveo series Alex Forencich 2025-02-25 11:34:26 -08:00
  • 4cdc4be47e example/ADM_PCIE_9V3: Testbench cleanup Alex Forencich 2025-02-24 21:42:23 -08:00
  • ffe667b047 example/Nexus_K3P_Q: Add example design for Cisco Nexus K3P-Q Alex Forencich 2025-02-24 21:39:26 -08:00
  • 8ffbd43e08 example/Nexus_K3P_S: Add example design for Cisco Nexus K35-S/K3P-S Alex Forencich 2025-02-24 21:04:42 -08:00
  • 916355ca8a eth: Add TX/RX polarity control to MAC+PHY+GT wrapper Alex Forencich 2025-02-24 17:17:23 -08:00
  • 7047cb5c4f eth: Tie off transceiver control signals during simulation Alex Forencich 2025-02-24 16:28:59 -08:00
  • 34266fe25d example/ZCU111: Add example design for ZCU111 Alex Forencich 2025-02-23 17:32:21 -08:00
  • 27033384d9 example: Update GPIO constraints Alex Forencich 2025-02-23 16:24:15 -08:00
  • 2fa899373e Update readme Alex Forencich 2025-02-23 14:13:42 -08:00
  • f424eb3f98 example/ADM-PCIE-9V3: Clean up makefiles Alex Forencich 2025-02-23 14:13:17 -08:00
  • aedf4d5c4c example/ZCU106: Fix width Alex Forencich 2025-02-23 14:12:57 -08:00
  • d2f6a94318 example/ZCU102: Add example design for ZCU102 Alex Forencich 2025-02-23 14:12:34 -08:00
  • 87b696b2aa example/ZCU106: Add example design for ZCU106 Alex Forencich 2025-02-23 12:12:28 -08:00
  • 182b44f7bc example/KCU105: Tie correct signals high Alex Forencich 2025-02-23 12:06:30 -08:00
  • 951f81680a example/ADM_PCIE_9V3: Add example design for ADM-PCIE-9V3 Alex Forencich 2025-02-23 00:49:41 -08:00
  • 9a8f311f2c example/KR160: Use correct MMCM primitive Alex Forencich 2025-02-23 00:36:13 -08:00
  • 75a746333e Update readme Alex Forencich 2025-02-22 23:36:13 -08:00
  • b6be624bdb example/KCU105: Add support for 10GBASE-R on KCU105 Alex Forencich 2025-02-22 23:15:24 -08:00
  • 4a439783f1 example/KR260: Add support for 10GBASE-R on KR260 Alex Forencich 2025-02-22 23:01:52 -08:00
  • db8b1fc27e example/VCU108: Add 25G MACs on QSFP28 port on VCU108 Alex Forencich 2025-02-22 22:33:54 -08:00
  • f0ec82a384 eth: Add MAC+PHY+GT wrapper for UltraScale Alex Forencich 2025-02-22 22:22:54 -08:00
  • 7613cae4f0 eth: Use 2D array for PFC config Alex Forencich 2025-02-22 22:08:43 -08:00
  • 7f2ecf9b49 eth: Implement RX sequence error reporting in MAC+PHY module Alex Forencich 2025-02-22 10:16:32 -08:00
  • 422c54229e eth: Split block type checks in MAC+PHY to reduce fanin Alex Forencich 2025-02-22 10:02:08 -08:00
  • 8f6a99112b eth: Add missing block types to MAC+PHY logic Alex Forencich 2025-02-22 09:55:28 -08:00
  • 6a294cef2c Use string type for string parameters Alex Forencich 2025-02-21 19:14:28 -08:00
  • 6154506c0a axis: Use reset synchronizer module in AXI stream async FIFO Alex Forencich 2025-02-20 12:44:23 -08:00
  • 17f3613ca4 eth: Clean up function definitions Alex Forencich 2025-02-20 12:21:33 -08:00
  • e388cb22c6 example/KR260: Update readme Alex Forencich 2025-02-20 10:21:49 -08:00
  • 650da9c972 example/HTG940: Add example design for HTG940 Alex Forencich 2025-02-20 10:20:15 -08:00
  • 152b5aeed5 example/KC705: Update readme Alex Forencich 2025-02-19 13:24:31 -08:00
  • 4db3ee5cd5 example/KR260: Update readme Alex Forencich 2025-02-19 12:03:53 -08:00
  • a56a33abc9 examples: Add notes on required licenses Alex Forencich 2025-02-19 12:02:07 -08:00
  • d5ed74431a example/KR260: Add example design for KR260 Alex Forencich 2025-02-19 10:59:15 -08:00
  • ae6f22e4da example/KCU105: Fix MMCM config Alex Forencich 2025-02-18 20:10:25 -08:00
  • 8241f33d47 example/VCU108: Example design cleanup Alex Forencich 2025-02-18 18:13:10 -08:00
  • a4025a1ead example/KC705: Example design cleanup Alex Forencich 2025-02-18 18:12:54 -08:00
  • 2e35f5b5ff example/KCU105: Add example design for KCU105 Alex Forencich 2025-02-18 18:08:25 -08:00
  • c7b79f9afb example/VCU108: Add example design for VCU108 Alex Forencich 2025-02-18 15:14:36 -08:00
  • daa5ca38af example/KC705: Fix MMCM notes Alex Forencich 2025-02-18 14:26:22 -08:00
  • 53688afeb5 example/KC705: Add example design for Xilinx KC705 Alex Forencich 2025-02-18 09:45:36 -08:00
  • 36ea9fb8d4 example/Arty: Clean up Arty example design Alex Forencich 2025-02-18 00:55:08 -08:00
  • db183c7bdd Add test durations for pytest-split Alex Forencich 2025-02-17 18:10:01 -08:00
  • 6577d016e5 Run example design testbenches in CI Alex Forencich 2025-02-17 00:26:06 -08:00
  • 2c6fac0b9d Update readme Alex Forencich 2025-02-17 00:13:51 -08:00
  • dd2a0d1bf3 example: Add example design for Arty A7 Alex Forencich 2025-02-17 00:13:06 -08:00
  • c6ca108392 eth: Clean up testbench clocking Alex Forencich 2025-02-16 22:45:19 -08:00
  • 689cd34739 eth: Add additional Ethernet MAC-related timing constraints Alex Forencich 2025-02-16 22:30:15 -08:00
  • 1112545d0a Update readme Alex Forencich 2025-02-16 22:22:43 -08:00
  • 94dba88560 eth: Add RGMII Ethernet MAC with FIFOs module and testbench Alex Forencich 2025-02-16 22:17:42 -08:00
  • 255b26d2f2 eth: Add GMII Ethernet MAC with FIFOs module and testbench Alex Forencich 2025-02-16 22:17:22 -08:00
  • baa5f72a6c eth: Add MII Ethernet MAC with FIFOs module and testbench Alex Forencich 2025-02-16 22:16:54 -08:00
  • ffaf05f2d1 eth: Add RGMII Ethernet MAC module and testbench Alex Forencich 2025-02-16 22:05:59 -08:00
  • fab49d1435 eth: Add RGMII PHY interface module Alex Forencich 2025-02-16 21:50:42 -08:00
  • c0583aaff5 eth: Add GMII Ethernet MAC module and testbench Alex Forencich 2025-02-16 21:37:12 -08:00
  • 1dc5463f00 eth: Add GMII PHY interface module Alex Forencich 2025-02-16 21:34:49 -08:00
  • 175230eeaf eth: Add MII Ethernet MAC module and testbench Alex Forencich 2025-02-16 20:46:31 -08:00
  • af912cc849 eth: Add MII PHY interface module Alex Forencich 2025-02-16 20:05:41 -08:00
  • da7fe065cc io: Rework generic ODDR implementation Alex Forencich 2025-02-16 19:27:56 -08:00
  • d01a90298c eth: Use correct clock for TX completions in MAC + FIFO testbenches Alex Forencich 2025-02-16 18:59:18 -08:00
  • 5c8037093b eth: Remove unnecessary PTP_TS_FMT_TOD parameter in 1G MAC module Alex Forencich 2025-02-16 18:06:41 -08:00
  • e3d8ad8d36 io: Add source-synchronous IO modules Alex Forencich 2025-02-16 15:44:34 -08:00
  • e18a2b3457 io: Add generic IDDR and ODDR modules Alex Forencich 2025-02-16 15:41:56 -08:00
  • 51d6919622 ptp: Add timing constraints for PTP components Alex Forencich 2025-02-16 11:29:57 -08:00
  • d048a8d7c7 Update readme Alex Forencich 2025-02-13 22:23:57 -08:00
  • 9ad43f3433 Update readme Alex Forencich 2025-02-13 22:13:01 -08:00
  • fc1e0efad7 ptp: Add PTP TD rel2tod timestamp reconstruction module and testbench Alex Forencich 2025-02-13 22:07:46 -08:00
  • ad0d44616b ptp: Add PTP TD leaf clock module and testbench Alex Forencich 2025-02-13 20:18:17 -08:00
  • 68c547b219 ptp: Minor cleanup in PTP CDC module Alex Forencich 2025-02-13 20:17:21 -08:00
  • 2eaa2f64a2 ptp: Add PTP TD PHC module and testbench Alex Forencich 2025-02-13 17:50:16 -08:00
  • 38a150b87a ptp: Add PTP period output module and testbench Alex Forencich 2025-02-13 17:06:46 -08:00
  • d1578513c8 Update readme Alex Forencich 2025-02-13 13:51:25 -08:00
  • 2abe774f8a eth: Add 10G Ethernet MAC+PHY module with FIFOs and testbench Alex Forencich 2025-02-13 13:48:54 -08:00
  • 90650aee69 eth: Add 10G Ethernet MAC module with FIFOs and testbench Alex Forencich 2025-02-13 13:47:54 -08:00
  • d76e810033 axis: Fix parameter sizing in AXI stream FIFOs Alex Forencich 2025-02-13 13:46:56 -08:00
  • f356fad6fe ptp: Add PTP clock CDC module and testbench Alex Forencich 2025-02-13 12:49:42 -08:00
  • 17b4c37a1e ptp: Add PTP clock module and testbench Alex Forencich 2025-02-13 10:52:27 -08:00
  • 8a67eaa220 eth: Clean up testbench parameters Alex Forencich 2025-02-11 22:35:18 -08:00
  • 04b73e7ddf eth: Add 1G Ethernet MAC module with FIFOs and testbench Alex Forencich 2025-02-11 22:12:57 -08:00
  • 8f8572bdee eth: Add taxi_axis_if to MAC file list files Alex Forencich 2025-02-11 15:54:15 -08:00
  • 2616e3f3e3 eth: Add 10G Ethernet combined MAC+PHY module and testbench Alex Forencich 2025-02-08 21:40:50 -08:00
  • 0ddb89b18f eth: Add 10G Ethernet MAC module and testbench Alex Forencich 2025-02-08 21:26:03 -08:00
  • fa73f9c1d5 eth: Add 1G Ethernet MAC module and testbench Alex Forencich 2025-02-08 21:25:48 -08:00
  • 8d3d703656 eth: Add MAC control modules Alex Forencich 2025-02-08 19:59:11 -08:00
  • 96e348ac84 eth: Invert TX completion output control Alex Forencich 2025-02-07 23:24:28 -08:00