557 lines
12 KiB
Systemverilog
557 lines
12 KiB
Systemverilog
// SPDX-License-Identifier: MIT
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/*
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Copyright (c) 2014-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* FPGA top-level module
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*/
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module fpga #
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(
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// simulation (set to avoid vendor primitives)
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parameter logic SIM = 1'b0,
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// vendor ("GENERIC", "XILINX", "ALTERA")
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parameter string VENDOR = "XILINX",
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// device family
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parameter string FAMILY = "kintex7",
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// Use 90 degree clock for RGMII transmit
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parameter logic USE_CLK90 = 1'b1,
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// BASE-T PHY type (GMII, RGMII)
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parameter BASET_PHY_TYPE = "GMII",
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// SFP rate selection (0 for 1G, 1 for 10G)
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parameter logic SFP_RATE = 1'b1,
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// Invert SFP data pins
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parameter logic SFP_INVERT = 1'b1,
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// 10G MAC configuration
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parameter logic CFG_LOW_LATENCY = 1'b1,
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parameter logic COMBINED_MAC_PCS = 1'b1
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)
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(
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/*
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* Clock: 200MHz
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* Reset: Push button, active high
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*/
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input wire logic clk_200mhz_p,
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input wire logic clk_200mhz_n,
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input wire logic reset,
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/*
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* GPIO
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*/
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input wire logic btnu,
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input wire logic btnl,
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input wire logic btnd,
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input wire logic btnr,
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input wire logic btnc,
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input wire logic [3:0] sw,
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output wire logic [7:0] led,
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/*
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* UART: 115200 bps, 8N1
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*/
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input wire logic uart_rxd,
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output wire logic uart_txd,
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input wire logic uart_rts,
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output wire logic uart_cts,
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/*
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* I2C
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*/
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inout wire logic i2c_scl,
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inout wire logic i2c_sda,
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output wire logic i2c_mux_reset,
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/*
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* Ethernet: SFP+
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*/
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input wire logic sfp_rx_p,
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input wire logic sfp_rx_n,
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output wire logic sfp_tx_p,
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output wire logic sfp_tx_n,
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input wire logic sfp_mgt_refclk_p,
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input wire logic sfp_mgt_refclk_n,
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output wire logic si5324_rst,
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input wire logic si5324_int,
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output wire logic sfp_tx_disable_b,
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/*
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* Ethernet: 1000BASE-T GMII or RGMII
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*/
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input wire logic phy_rx_clk,
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input wire logic [7:0] phy_rxd,
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input wire logic phy_rx_dv,
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input wire logic phy_rx_er,
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output wire logic phy_gtx_clk,
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input wire logic phy_tx_clk,
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output wire logic [7:0] phy_txd,
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output wire logic phy_tx_en,
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output wire logic phy_tx_er,
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output wire logic phy_reset_n,
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input wire logic phy_int_n
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);
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// Clock and reset
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wire clk_200mhz_ibufg;
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// Internal 125 MHz clock
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wire clk_mmcm_out;
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wire clk_int;
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wire clk90_mmcm_out;
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wire clk90_int;
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wire rst_int;
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wire clk_200mhz_mmcm_out;
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wire clk_200mhz_int;
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wire mmcm_rst = reset;
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wire mmcm_locked;
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wire mmcm_clkfb;
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IBUFGDS
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clk_200mhz_ibufgds_inst(
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.I(clk_200mhz_p),
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.IB(clk_200mhz_n),
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.O(clk_200mhz_ibufg)
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);
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// MMCM instance
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MMCME2_BASE #(
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// 200 MHz input
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.CLKIN1_PERIOD(5.0),
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.REF_JITTER1(0.010),
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// 200 MHz input / 1 = 200 MHz PFD (range 10 MHz to 500 MHz)
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.DIVCLK_DIVIDE(1),
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// 200 MHz PFD * 5 = 1000 MHz VCO (range 600 MHz to 1440 MHz)
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.CLKFBOUT_MULT_F(5),
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.CLKFBOUT_PHASE(0),
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// 1000 MHz VCO / 8 = 125 MHz, 0 degrees
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.CLKOUT0_DIVIDE_F(8),
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0),
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// 1000 MHz VCO / 8 = 125 MHz, 90 degrees
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.CLKOUT1_DIVIDE(8),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT1_PHASE(90),
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// 1000 MHz VCO / 5 = 200 MHz, 0 degrees
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.CLKOUT2_DIVIDE(5),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT2_PHASE(0),
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// Not used
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.CLKOUT3_DIVIDE(1),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT3_PHASE(0),
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// Not used
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.CLKOUT4_DIVIDE(1),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT4_PHASE(0),
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.CLKOUT4_CASCADE("FALSE"),
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// Not used
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.CLKOUT5_DIVIDE(1),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT5_PHASE(0),
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// Not used
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.CLKOUT6_DIVIDE(1),
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.CLKOUT6_DUTY_CYCLE(0.5),
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.CLKOUT6_PHASE(0),
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// optimized bandwidth
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.BANDWIDTH("OPTIMIZED"),
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// don't wait for lock during startup
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.STARTUP_WAIT("FALSE")
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)
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clk_mmcm_inst (
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// 200 MHz input
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.CLKIN1(clk_200mhz_ibufg),
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// direct clkfb feeback
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.CLKFBIN(mmcm_clkfb),
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.CLKFBOUT(mmcm_clkfb),
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.CLKFBOUTB(),
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// 125 MHz, 0 degrees
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.CLKOUT0(clk_mmcm_out),
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.CLKOUT0B(),
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// 125 MHz, 90 degrees
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.CLKOUT1(clk90_mmcm_out),
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.CLKOUT1B(),
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// 200 MHz, 0 degrees
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.CLKOUT2(clk_200mhz_mmcm_out),
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.CLKOUT2B(),
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// Not used
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.CLKOUT3(),
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.CLKOUT3B(),
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// Not used
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.CLKOUT4(),
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// Not used
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.CLKOUT5(),
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// Not used
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.CLKOUT6(),
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// reset input
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.RST(mmcm_rst),
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// don't power down
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.PWRDWN(1'b0),
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// locked output
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.LOCKED(mmcm_locked)
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);
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BUFG
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clk_bufg_inst (
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.I(clk_mmcm_out),
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.O(clk_int)
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);
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BUFG
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clk90_bufg_inst (
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.I(clk90_mmcm_out),
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.O(clk90_int)
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);
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BUFG
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clk_200mhz_bufg_inst (
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.I(clk_200mhz_mmcm_out),
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.O(clk_200mhz_int)
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);
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taxi_sync_reset #(
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.N(4)
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)
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sync_reset_inst (
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.clk(clk_int),
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.rst(~mmcm_locked),
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.out(rst_int)
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);
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// GPIO
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wire btnu_int;
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wire btnl_int;
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wire btnd_int;
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wire btnr_int;
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wire btnc_int;
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wire [3:0] sw_int;
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taxi_debounce_switch #(
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.WIDTH(9),
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.N(4),
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.RATE(125000)
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)
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debounce_switch_inst (
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.clk(clk_int),
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.rst(rst_int),
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.in({btnu,
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btnl,
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btnd,
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btnr,
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btnc,
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sw}),
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.out({btnu_int,
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btnl_int,
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btnd_int,
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btnr_int,
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btnc_int,
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sw_int})
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);
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wire uart_rxd_int;
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wire uart_rts_int;
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taxi_sync_signal #(
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.WIDTH(2),
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.N(2)
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)
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sync_signal_inst (
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.clk(clk_int),
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.in({uart_rxd, uart_rts}),
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.out({uart_rxd_int, uart_rts_int})
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);
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// I2C
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wire i2c_scl_i;
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wire i2c_scl_o;
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wire i2c_sda_i;
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wire i2c_sda_o;
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assign i2c_scl_i = i2c_scl;
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assign i2c_scl = i2c_scl_o ? 1'bz : 1'b0;
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assign i2c_sda_i = i2c_sda;
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assign i2c_sda = i2c_sda_o ? 1'bz : 1'b0;
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wire i2c_init_scl_i = i2c_scl_i;
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wire i2c_init_scl_o;
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wire i2c_init_sda_i = i2c_sda_i;
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wire i2c_init_sda_o;
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wire i2c_int_scl_i = i2c_scl_i;
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wire i2c_int_scl_o;
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wire i2c_int_sda_i = i2c_sda_i;
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wire i2c_int_sda_o;
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assign i2c_scl_o = i2c_init_scl_o & i2c_int_scl_o;
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assign i2c_sda_o = i2c_init_sda_o & i2c_int_sda_o;
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// Si5324 init
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taxi_axis_if #(.DATA_W(12)) si5324_i2c_cmd();
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taxi_axis_if #(.DATA_W(8)) si5324_i2c_tx();
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taxi_axis_if #(.DATA_W(8)) si5324_i2c_rx();
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assign si5324_i2c_rx.tready = 1'b1;
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wire si5324_i2c_busy;
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assign si5324_rst = ~rst_int;
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taxi_i2c_master
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si5324_i2c_master_inst (
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.clk(clk_int),
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.rst(rst_int),
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/*
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* Host interface
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*/
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.s_axis_cmd(si5324_i2c_cmd),
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.s_axis_tx(si5324_i2c_tx),
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.m_axis_rx(si5324_i2c_rx),
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/*
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* I2C interface
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*/
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.scl_i(i2c_init_scl_i),
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.scl_o(i2c_init_scl_o),
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.sda_i(i2c_init_sda_i),
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.sda_o(i2c_init_sda_o),
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/*
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* Status
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*/
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.busy(),
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.bus_control(),
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.bus_active(),
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.missed_ack(),
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/*
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* Configuration
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*/
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.prescale(SIM ? 32 : 312),
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.stop_on_idle(1)
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);
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si5324_i2c_init #(
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.SIM_SPEEDUP(SIM)
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)
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si5324_i2c_init_inst (
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.clk(clk_int),
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.rst(rst_int),
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/*
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* I2C master interface
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*/
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.m_axis_cmd(si5324_i2c_cmd),
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.m_axis_tx(si5324_i2c_tx),
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/*
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* Status
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*/
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.busy(si5324_i2c_busy),
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/*
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* Configuration
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*/
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.start(1'b1)
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);
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wire phy_rgmii_rx_clk_int;
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wire [3:0] phy_rgmii_rxd_int;
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wire phy_rgmii_rx_ctl_int;
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wire phy_rgmii_tx_clk_int;
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wire [3:0] phy_rgmii_txd_int;
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wire phy_rgmii_tx_ctl_int;
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wire phy_gmii_rx_clk_int;
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wire [7:0] phy_gmii_rxd_int;
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wire phy_gmii_rx_dv_int;
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wire phy_gmii_rx_er_int;
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wire phy_gmii_gtx_clk_int;
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wire phy_gmii_tx_clk_int;
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wire [7:0] phy_gmii_txd_int;
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wire phy_gmii_tx_en_int;
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wire phy_gmii_tx_er_int;
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if (BASET_PHY_TYPE == "RGMII") begin : phy_if
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assign phy_rgmii_rx_clk_int = phy_rx_clk;
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// IODELAY elements for RGMII interface to PHY
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IDELAYCTRL
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idelayctrl_inst (
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.REFCLK(clk_200mhz_int),
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.RST(rst_int),
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.RDY()
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);
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for (genvar n = 0; n < 4; n = n + 1) begin : phy_rxd_idelay_bit
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IDELAYE2 #(
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.IDELAY_TYPE("FIXED")
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)
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idelay_inst (
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.IDATAIN(phy_rxd[n]),
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.DATAOUT(phy_rgmii_rxd_int[n]),
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.DATAIN(1'b0),
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.C(1'b0),
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.CE(1'b0),
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.INC(1'b0),
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.CINVCTRL(1'b0),
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.CNTVALUEIN(5'd0),
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.CNTVALUEOUT(),
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.LD(1'b0),
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.LDPIPEEN(1'b0),
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.REGRST(1'b0)
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);
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end
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IDELAYE2 #(
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.IDELAY_TYPE("FIXED")
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)
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phy_rx_ctl_idelay (
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.IDATAIN(phy_rx_dv),
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.DATAOUT(phy_rgmii_rx_ctl_int),
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.DATAIN(1'b0),
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.C(1'b0),
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.CE(1'b0),
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.INC(1'b0),
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.CINVCTRL(1'b0),
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.CNTVALUEIN(5'd0),
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.CNTVALUEOUT(),
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.LD(1'b0),
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.LDPIPEEN(1'b0),
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.REGRST(1'b0)
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);
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assign phy_gtx_clk = phy_rgmii_tx_clk_int;
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assign phy_txd[3:0] = phy_rgmii_txd_int;
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assign phy_tx_en = phy_rgmii_tx_ctl_int;
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assign phy_txd[7:4] = '0;
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assign phy_tx_er = 1'b0;
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assign phy_gmii_rx_clk_int = 1'b0;
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assign phy_gmii_rxd_int = '0;
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assign phy_gmii_rx_dv_int = 1'b0;
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assign phy_gmii_rx_er_int = 1'b0;
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assign phy_gmii_tx_clk_int = 1'b0;
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end else begin : phy_if
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assign phy_rgmii_rx_clk_int = 1'b0;
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assign phy_rgmii_rxd_int = '0;
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assign phy_rgmii_rx_ctl_int = 1'b0;
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assign phy_gmii_rx_clk_int = phy_rx_clk;
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assign phy_gmii_rxd_int = phy_rxd;
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assign phy_gmii_rx_dv_int = phy_rx_dv;
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assign phy_gmii_rx_er_int = phy_rx_er;
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assign phy_gtx_clk = phy_gmii_gtx_clk_int;
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assign phy_gmii_tx_clk_int = phy_tx_clk;
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assign phy_txd = phy_gmii_txd_int;
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assign phy_tx_en = phy_gmii_tx_en_int;
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assign phy_tx_er = phy_gmii_tx_er_int;
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end
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fpga_core #(
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.SIM(SIM),
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.VENDOR(VENDOR),
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.FAMILY(FAMILY),
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.USE_CLK90(USE_CLK90),
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.BASET_PHY_TYPE(BASET_PHY_TYPE),
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.SFP_INVERT(SFP_INVERT),
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.CFG_LOW_LATENCY(CFG_LOW_LATENCY),
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.COMBINED_MAC_PCS(COMBINED_MAC_PCS)
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)
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core_inst (
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/*
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* Clock: 125MHz
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* Synchronous reset
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*/
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.clk(clk_int),
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.clk90(clk90_int),
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.rst(rst_int),
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/*
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* GPIO
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*/
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.btnu(btnu_int),
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.btnl(btnl_int),
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.btnd(btnd_int),
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.btnr(btnr_int),
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.btnc(btnc_int),
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.sw(sw_int),
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.led(led),
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/*
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* UART: 115200 bps, 8N1
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*/
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.uart_rxd(uart_rxd_int),
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.uart_txd(uart_txd),
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.uart_rts(uart_rts_int),
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.uart_cts(uart_cts),
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/*
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* I2C
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*/
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.i2c_scl_i(i2c_int_scl_i),
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.i2c_scl_o(i2c_int_scl_o),
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.i2c_sda_i(i2c_int_sda_i),
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.i2c_sda_o(i2c_int_sda_o),
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/*
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* Ethernet: SFP+
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*/
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.sfp_rx_p(sfp_rx_p),
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.sfp_rx_n(sfp_rx_n),
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.sfp_tx_p(sfp_tx_p),
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.sfp_tx_n(sfp_tx_n),
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.sfp_mgt_refclk_p(sfp_mgt_refclk_p),
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.sfp_mgt_refclk_n(sfp_mgt_refclk_n),
|
|
|
|
.sfp_tx_disable_b(sfp_tx_disable_b),
|
|
|
|
/*
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|
* Ethernet: 1000BASE-T GMII/RGMII/SGMII
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|
*/
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|
.phy_rgmii_rx_clk(phy_rgmii_rx_clk_int),
|
|
.phy_rgmii_rxd(phy_rgmii_rxd_int),
|
|
.phy_rgmii_rx_ctl(phy_rgmii_rx_ctl_int),
|
|
.phy_rgmii_tx_clk(phy_rgmii_tx_clk_int),
|
|
.phy_rgmii_txd(phy_rgmii_txd_int),
|
|
.phy_rgmii_tx_ctl(phy_rgmii_tx_ctl_int),
|
|
|
|
.phy_gmii_rx_clk(phy_gmii_rx_clk_int),
|
|
.phy_gmii_rxd(phy_gmii_rxd_int),
|
|
.phy_gmii_rx_dv(phy_gmii_rx_dv_int),
|
|
.phy_gmii_rx_er(phy_gmii_rx_er_int),
|
|
.phy_gmii_gtx_clk(phy_gmii_gtx_clk_int),
|
|
.phy_gmii_tx_clk(phy_gmii_tx_clk_int),
|
|
.phy_gmii_txd(phy_gmii_txd_int),
|
|
.phy_gmii_tx_en(phy_gmii_tx_en_int),
|
|
.phy_gmii_tx_er(phy_gmii_tx_er_int),
|
|
|
|
.phy_reset_n(phy_reset_n),
|
|
.phy_int_n(phy_int_n)
|
|
);
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|
|
|
endmodule
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|
|
|
`resetall
|