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axi: Add AXI to AXI lite adapter module and testbench

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-08-30 21:11:20 -07:00
parent 94a821192c
commit 0080125120
8 changed files with 1959 additions and 0 deletions
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1
README.md
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@@ -26,6 +26,7 @@ To facilitate the dual-license model, contributions to the project can only be a
* AXI * AXI
* SV interface for AXI * SV interface for AXI
* AXI to AXI lite adapter
* Register slice * Register slice
* Width converter * Width converter
* Single-port RAM * Single-port RAM

5
src/axi/rtl/taxi_axi_axil_adapter.f Normal file
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taxi_axi_axil_adapter.sv
taxi_axi_axil_adapter_wr.sv
taxi_axi_axil_adapter_rd.sv
taxi_axi_if.sv
taxi_axil_if.sv

82
src/axi/rtl/taxi_axi_axil_adapter.sv Normal file
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// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2019-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4 to AXI4-Lite adapter
*/
module taxi_axi_axil_adapter #
(
// When adapting to a wider bus, re-pack full-width burst instead of passing through narrow burst if possible
parameter logic CONVERT_BURST = 1'b1,
// When adapting to a wider bus, re-pack all bursts instead of passing through narrow burst if possible
parameter logic CONVERT_NARROW_BURST = 1'b0
)
(
input wire logic clk,
input wire logic rst,
/*
* AXI4 slave interface
*/
taxi_axi_if.wr_slv s_axi_wr,
taxi_axi_if.rd_slv s_axi_rd,
/*
* AXI4-Lite master interface
*/
taxi_axil_if.wr_mst m_axil_wr,
taxi_axil_if.rd_mst m_axil_rd
);
taxi_axi_axil_adapter_wr #(
.CONVERT_BURST(CONVERT_BURST),
.CONVERT_NARROW_BURST(CONVERT_NARROW_BURST)
)
axi_axil_adapter_wr_inst (
.clk(clk),
.rst(rst),
/*
* AXI4 slave interface
*/
.s_axi_wr(s_axi_wr),
/*
* AXI4-Lite master interface
*/
.m_axil_wr(m_axil_wr)
);
taxi_axi_axil_adapter_rd #(
.CONVERT_BURST(CONVERT_BURST),
.CONVERT_NARROW_BURST(CONVERT_NARROW_BURST)
)
axi_axil_adapter_rd_inst (
.clk(clk),
.rst(rst),
/*
* AXI4 slave interface
*/
.s_axi_rd(s_axi_rd),
/*
* AXI4-Lite master interface
*/
.m_axil_rd(m_axil_rd)
);
endmodule
`resetall

663
src/axi/rtl/taxi_axi_axil_adapter_rd.sv Normal file
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@@ -0,0 +1,663 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2019-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4 to AXI4-Lite adapter (read)
*/
module taxi_axi_axil_adapter_rd #
(
// When adapting to a wider bus, re-pack full-width burst instead of passing through narrow burst if possible
parameter logic CONVERT_BURST = 1'b1,
// When adapting to a wider bus, re-pack all bursts instead of passing through narrow burst if possible
parameter logic CONVERT_NARROW_BURST = 1'b0
)
(
input wire logic clk,
input wire logic rst,
/*
* AXI4 slave interface
*/
taxi_axi_if.rd_slv s_axi_rd,
/*
* AXI4-Lite master interface
*/
taxi_axil_if.rd_mst m_axil_rd
);
// extract parameters
localparam AXI_DATA_W = s_axi_rd.DATA_W;
localparam ADDR_W = s_axi_rd.ADDR_W;
localparam CL_ADDR_W = $clog2(ADDR_W);
localparam AXI_STRB_W = s_axi_rd.STRB_W;
localparam AXI_ID_W = s_axi_rd.ID_W;
localparam logic ARUSER_EN = s_axi_rd.ARUSER_EN && m_axil_rd.ARUSER_EN;
localparam ARUSER_W = s_axi_rd.ARUSER_W;
localparam logic RUSER_EN = s_axi_rd.RUSER_EN && m_axil_rd.RUSER_EN;
localparam RUSER_W = s_axi_rd.RUSER_W;
localparam AXIL_DATA_W = m_axil_rd.DATA_W;
localparam AXIL_STRB_W = m_axil_rd.STRB_W;
localparam AXI_ADDR_BIT_OFFSET = $clog2(AXI_STRB_W);
localparam AXIL_ADDR_BIT_OFFSET = $clog2(AXIL_STRB_W);
localparam AXI_BYTE_LANES = AXI_STRB_W;
localparam AXIL_BYTE_LANES = AXIL_STRB_W;
localparam AXI_BYTE_SIZE = AXI_DATA_W/AXI_BYTE_LANES;
localparam AXIL_BYTE_SIZE = AXIL_DATA_W/AXIL_BYTE_LANES;
localparam logic [2:0] AXI_BURST_SIZE = 3'($clog2(AXI_BYTE_LANES));
localparam logic [2:0] AXIL_BURST_SIZE = 3'($clog2(AXIL_BYTE_LANES));
// check configuration
if (AXI_BYTE_SIZE * AXI_STRB_W != AXI_DATA_W)
$fatal(0, "Error: AXI slave interface data width not evenly divisible (instance %m)");
if (AXIL_BYTE_SIZE * AXIL_STRB_W != AXIL_DATA_W)
$fatal(0, "Error: AXI lite master interface data width not evenly divisible (instance %m)");
if (AXI_BYTE_SIZE != AXIL_BYTE_SIZE)
$fatal(0, "Error: byte size mismatch (instance %m)");
if (2**$clog2(AXI_BYTE_LANES) != AXI_BYTE_LANES)
$fatal(0, "Error: AXI slave interface byte lane count must be even power of two (instance %m)");
if (2**$clog2(AXIL_BYTE_LANES) != AXIL_BYTE_LANES)
$fatal(0, "Error: AXI lite master interface byte lane count must be even power of two (instance %m)");
if (AXIL_BYTE_LANES == AXI_BYTE_LANES) begin : translate
// same width; translate
// output bus is wider
localparam EXPAND = AXIL_BYTE_LANES > AXI_BYTE_LANES;
localparam DATA_W = EXPAND ? AXIL_DATA_W : AXI_DATA_W;
localparam STRB_W = EXPAND ? AXIL_STRB_W : AXI_STRB_W;
// required number of segments in wider bus
localparam SEG_COUNT = EXPAND ? (AXIL_BYTE_LANES / AXI_BYTE_LANES) : (AXI_BYTE_LANES / AXIL_BYTE_LANES);
// data width and keep width per segment
localparam SEG_DATA_W = DATA_W / SEG_COUNT;
localparam SEG_STRB_W = STRB_W / SEG_COUNT;
localparam [0:0]
STATE_IDLE = 1'd0,
STATE_DATA = 1'd1;
logic [0:0] state_reg = STATE_IDLE, state_next;
logic [AXI_ID_W-1:0] id_reg = '0, id_next;
logic [ADDR_W-1:0] addr_reg = '0, addr_next;
logic [DATA_W-1:0] data_reg = '0, data_next;
logic [1:0] resp_reg = 2'd0, resp_next;
logic [7:0] burst_reg = 8'd0, burst_next;
logic [2:0] burst_size_reg = 3'd0, burst_size_next;
logic [7:0] master_burst_reg = 8'd0, master_burst_next;
logic [2:0] master_burst_size_reg = 3'd0, master_burst_size_next;
logic s_axi_arready_reg = 1'b0, s_axi_arready_next;
logic [AXI_ID_W-1:0] s_axi_rid_reg = '0, s_axi_rid_next;
logic [AXI_DATA_W-1:0] s_axi_rdata_reg = '0, s_axi_rdata_next;
logic [1:0] s_axi_rresp_reg = 2'd0, s_axi_rresp_next;
logic s_axi_rlast_reg = 1'b0, s_axi_rlast_next;
logic s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;
logic [ADDR_W-1:0] m_axil_araddr_reg = '0, m_axil_araddr_next;
logic [2:0] m_axil_arprot_reg = 3'd0, m_axil_arprot_next;
logic m_axil_arvalid_reg = 1'b0, m_axil_arvalid_next;
logic m_axil_rready_reg = 1'b0, m_axil_rready_next;
assign s_axi_rd.arready = s_axi_arready_reg;
assign s_axi_rd.rid = s_axi_rid_reg;
assign s_axi_rd.rdata = s_axi_rdata_reg;
assign s_axi_rd.rresp = s_axi_rresp_reg;
assign s_axi_rd.rlast = s_axi_rlast_reg;
assign s_axi_rd.rvalid = s_axi_rvalid_reg;
assign m_axil_rd.araddr = m_axil_araddr_reg;
assign m_axil_rd.arprot = m_axil_arprot_reg;
assign m_axil_rd.arvalid = m_axil_arvalid_reg;
assign m_axil_rd.rready = m_axil_rready_reg;
always_comb begin
state_next = STATE_IDLE;
id_next = id_reg;
addr_next = addr_reg;
data_next = data_reg;
resp_next = resp_reg;
burst_next = burst_reg;
burst_size_next = burst_size_reg;
master_burst_next = master_burst_reg;
master_burst_size_next = master_burst_size_reg;
s_axi_arready_next = 1'b0;
s_axi_rid_next = s_axi_rid_reg;
s_axi_rdata_next = s_axi_rdata_reg;
s_axi_rresp_next = s_axi_rresp_reg;
s_axi_rlast_next = s_axi_rlast_reg;
s_axi_rvalid_next = s_axi_rvalid_reg && !s_axi_rd.rready;
m_axil_araddr_next = m_axil_araddr_reg;
m_axil_arprot_next = m_axil_arprot_reg;
m_axil_arvalid_next = m_axil_arvalid_reg && !m_axil_rd.arready;
m_axil_rready_next = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state; wait for new burst
s_axi_arready_next = !m_axil_rd.arvalid;
if (s_axi_rd.arready && s_axi_rd.arvalid) begin
s_axi_arready_next = 1'b0;
id_next = s_axi_rd.arid;
m_axil_araddr_next = s_axi_rd.araddr;
addr_next = s_axi_rd.araddr;
burst_next = s_axi_rd.arlen;
burst_size_next = s_axi_rd.arsize;
m_axil_arprot_next = s_axi_rd.arprot;
m_axil_arvalid_next = 1'b1;
m_axil_rready_next = 1'b0;
state_next = STATE_DATA;
end else begin
state_next = STATE_IDLE;
end
end
STATE_DATA: begin
// data state; transfer read data
m_axil_rready_next = !s_axi_rd.rvalid && !m_axil_rd.arvalid;
if (m_axil_rd.rready && m_axil_rd.rvalid) begin
s_axi_rid_next = id_reg;
s_axi_rdata_next = m_axil_rd.rdata;
s_axi_rresp_next = m_axil_rd.rresp;
s_axi_rlast_next = 1'b0;
s_axi_rvalid_next = 1'b1;
burst_next = burst_reg - 1;
addr_next = addr_reg + (1 << burst_size_reg);
if (burst_reg == 0) begin
// last data word, return to idle
m_axil_rready_next = 1'b0;
s_axi_rlast_next = 1'b1;
s_axi_arready_next = !m_axil_rd.arvalid;
state_next = STATE_IDLE;
end else begin
// start new AXI lite read
m_axil_araddr_next = addr_next;
m_axil_arvalid_next = 1'b1;
m_axil_rready_next = 1'b0;
state_next = STATE_DATA;
end
end else begin
state_next = STATE_DATA;
end
end
endcase
end
always_ff @(posedge clk) begin
state_reg <= state_next;
id_reg <= id_next;
addr_reg <= addr_next;
data_reg <= data_next;
resp_reg <= resp_next;
burst_reg <= burst_next;
burst_size_reg <= burst_size_next;
master_burst_reg <= master_burst_next;
master_burst_size_reg <= master_burst_size_next;
s_axi_arready_reg <= s_axi_arready_next;
s_axi_rid_reg <= s_axi_rid_next;
s_axi_rdata_reg <= s_axi_rdata_next;
s_axi_rresp_reg <= s_axi_rresp_next;
s_axi_rlast_reg <= s_axi_rlast_next;
s_axi_rvalid_reg <= s_axi_rvalid_next;
m_axil_araddr_reg <= m_axil_araddr_next;
m_axil_arprot_reg <= m_axil_arprot_next;
m_axil_arvalid_reg <= m_axil_arvalid_next;
m_axil_rready_reg <= m_axil_rready_next;
if (rst) begin
state_reg <= STATE_IDLE;
s_axi_arready_reg <= 1'b0;
s_axi_rvalid_reg <= 1'b0;
m_axil_arvalid_reg <= 1'b0;
m_axil_rready_reg <= 1'b0;
end
end
end else if (AXIL_BYTE_LANES > AXI_BYTE_LANES) begin : upsize
// output is wider; upsize
// output bus is wider
localparam EXPAND = AXIL_BYTE_LANES > AXI_BYTE_LANES;
localparam DATA_W = EXPAND ? AXIL_DATA_W : AXI_DATA_W;
localparam STRB_W = EXPAND ? AXIL_STRB_W : AXI_STRB_W;
// required number of segments in wider bus
localparam SEG_COUNT = EXPAND ? (AXIL_BYTE_LANES / AXI_BYTE_LANES) : (AXI_BYTE_LANES / AXIL_BYTE_LANES);
// data width and keep width per segment
localparam SEG_DATA_W = DATA_W / SEG_COUNT;
localparam SEG_STRB_W = STRB_W / SEG_COUNT;
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_DATA = 2'd1,
STATE_DATA_READ = 2'd2,
STATE_DATA_SPLIT = 2'd3;
logic [1:0] state_reg = STATE_IDLE, state_next;
logic [AXI_ID_W-1:0] id_reg = '0, id_next;
logic [ADDR_W-1:0] addr_reg = '0, addr_next;
logic [DATA_W-1:0] data_reg = '0, data_next;
logic [1:0] resp_reg = 2'd0, resp_next;
logic [7:0] burst_reg = 8'd0, burst_next;
logic [2:0] burst_size_reg = 3'd0, burst_size_next;
logic [7:0] master_burst_reg = 8'd0, master_burst_next;
logic [2:0] master_burst_size_reg = 3'd0, master_burst_size_next;
logic s_axi_arready_reg = 1'b0, s_axi_arready_next;
logic [AXI_ID_W-1:0] s_axi_rid_reg = '0, s_axi_rid_next;
logic [AXI_DATA_W-1:0] s_axi_rdata_reg = '0, s_axi_rdata_next;
logic [1:0] s_axi_rresp_reg = 2'd0, s_axi_rresp_next;
logic s_axi_rlast_reg = 1'b0, s_axi_rlast_next;
logic s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;
logic [ADDR_W-1:0] m_axil_araddr_reg = '0, m_axil_araddr_next;
logic [2:0] m_axil_arprot_reg = 3'd0, m_axil_arprot_next;
logic m_axil_arvalid_reg = 1'b0, m_axil_arvalid_next;
logic m_axil_rready_reg = 1'b0, m_axil_rready_next;
assign s_axi_rd.arready = s_axi_arready_reg;
assign s_axi_rd.rid = s_axi_rid_reg;
assign s_axi_rd.rdata = s_axi_rdata_reg;
assign s_axi_rd.rresp = s_axi_rresp_reg;
assign s_axi_rd.rlast = s_axi_rlast_reg;
assign s_axi_rd.rvalid = s_axi_rvalid_reg;
assign m_axil_rd.araddr = m_axil_araddr_reg;
assign m_axil_rd.arprot = m_axil_arprot_reg;
assign m_axil_rd.arvalid = m_axil_arvalid_reg;
assign m_axil_rd.rready = m_axil_rready_reg;
always_comb begin
state_next = STATE_IDLE;
id_next = id_reg;
addr_next = addr_reg;
data_next = data_reg;
resp_next = resp_reg;
burst_next = burst_reg;
burst_size_next = burst_size_reg;
master_burst_next = master_burst_reg;
master_burst_size_next = master_burst_size_reg;
s_axi_arready_next = 1'b0;
s_axi_rid_next = s_axi_rid_reg;
s_axi_rdata_next = s_axi_rdata_reg;
s_axi_rresp_next = s_axi_rresp_reg;
s_axi_rlast_next = s_axi_rlast_reg;
s_axi_rvalid_next = s_axi_rvalid_reg && !s_axi_rd.rready;
m_axil_araddr_next = m_axil_araddr_reg;
m_axil_arprot_next = m_axil_arprot_reg;
m_axil_arvalid_next = m_axil_arvalid_reg && !m_axil_rd.arready;
m_axil_rready_next = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state; wait for new burst
s_axi_arready_next = !m_axil_rd.arvalid;
if (s_axi_rd.arready && s_axi_rd.arvalid) begin
s_axi_arready_next = 1'b0;
id_next = s_axi_rd.arid;
m_axil_araddr_next = s_axi_rd.araddr;
addr_next = s_axi_rd.araddr;
burst_next = s_axi_rd.arlen;
burst_size_next = s_axi_rd.arsize;
if (CONVERT_BURST && s_axi_rd.arcache[1] && (CONVERT_NARROW_BURST || s_axi_rd.arsize == AXI_BURST_SIZE)) begin
// split reads
// require CONVERT_BURST and arcache[1] set
master_burst_size_next = AXIL_BURST_SIZE;
state_next = STATE_DATA_READ;
end else begin
// output narrow burst
master_burst_size_next = s_axi_rd.arsize;
state_next = STATE_DATA;
end
m_axil_arprot_next = s_axi_rd.arprot;
m_axil_arvalid_next = 1'b1;
m_axil_rready_next = 1'b0;
end else begin
state_next = STATE_IDLE;
end
end
STATE_DATA: begin
m_axil_rready_next = !s_axi_rd.rvalid && !m_axil_rd.arvalid;
if (m_axil_rd.rready && m_axil_rd.rvalid) begin
s_axi_rid_next = id_reg;
s_axi_rdata_next = m_axil_rd.rdata[addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET] * AXI_DATA_W +: AXI_DATA_W];
s_axi_rresp_next = m_axil_rd.rresp;
s_axi_rlast_next = 1'b0;
s_axi_rvalid_next = 1'b1;
burst_next = burst_reg - 1;
addr_next = addr_reg + (1 << burst_size_reg);
if (burst_reg == 0) begin
// last data word, return to idle
m_axil_rready_next = 1'b0;
s_axi_rlast_next = 1'b1;
s_axi_arready_next = !m_axil_rd.arvalid;
state_next = STATE_IDLE;
end else begin
// start new AXI lite read
m_axil_araddr_next = addr_next;
m_axil_arvalid_next = 1'b1;
m_axil_rready_next = 1'b0;
state_next = STATE_DATA;
end
end else begin
state_next = STATE_DATA;
end
end
STATE_DATA_READ: begin
m_axil_rready_next = !s_axi_rd.rvalid && !m_axil_rd.arvalid;
if (m_axil_rd.rready && m_axil_rd.rvalid) begin
s_axi_rid_next = id_reg;
data_next = m_axil_rd.rdata;
resp_next = m_axil_rd.rresp;
s_axi_rdata_next = m_axil_rd.rdata[addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET] * AXI_DATA_W +: AXI_DATA_W];
s_axi_rresp_next = m_axil_rd.rresp;
s_axi_rlast_next = 1'b0;
s_axi_rvalid_next = 1'b1;
burst_next = burst_reg - 1;
addr_next = addr_reg + (1 << burst_size_reg);
if (burst_reg == 0) begin
m_axil_rready_next = 1'b0;
s_axi_arready_next = !m_axil_rd.arvalid;
s_axi_rlast_next = 1'b1;
state_next = STATE_IDLE;
end else if (addr_next[CL_ADDR_W'(master_burst_size_reg)] != addr_reg[CL_ADDR_W'(master_burst_size_reg)]) begin
// start new AXI lite read
m_axil_araddr_next = addr_next;
m_axil_arvalid_next = 1'b1;
m_axil_rready_next = 1'b0;
state_next = STATE_DATA_READ;
end else begin
m_axil_rready_next = 1'b0;
state_next = STATE_DATA_SPLIT;
end
end else begin
state_next = STATE_DATA_READ;
end
end
STATE_DATA_SPLIT: begin
m_axil_rready_next = 1'b0;
if (s_axi_rd.rready || !s_axi_rd.rvalid) begin
s_axi_rid_next = id_reg;
s_axi_rdata_next = data_reg[addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET] * AXI_DATA_W +: AXI_DATA_W];
s_axi_rresp_next = resp_reg;
s_axi_rlast_next = 1'b0;
s_axi_rvalid_next = 1'b1;
burst_next = burst_reg - 1;
addr_next = addr_reg + (1 << burst_size_reg);
if (burst_reg == 0) begin
s_axi_arready_next = !m_axil_rd.arvalid;
s_axi_rlast_next = 1'b1;
state_next = STATE_IDLE;
end else if (addr_next[CL_ADDR_W'(master_burst_size_reg)] != addr_reg[CL_ADDR_W'(master_burst_size_reg)]) begin
// start new AXI lite read
m_axil_araddr_next = addr_next;
m_axil_arvalid_next = 1'b1;
m_axil_rready_next = 1'b0;
state_next = STATE_DATA_READ;
end else begin
state_next = STATE_DATA_SPLIT;
end
end else begin
state_next = STATE_DATA_SPLIT;
end
end
endcase
end
always_ff @(posedge clk) begin
state_reg <= state_next;
id_reg <= id_next;
addr_reg <= addr_next;
data_reg <= data_next;
resp_reg <= resp_next;
burst_reg <= burst_next;
burst_size_reg <= burst_size_next;
master_burst_reg <= master_burst_next;
master_burst_size_reg <= master_burst_size_next;
s_axi_arready_reg <= s_axi_arready_next;
s_axi_rid_reg <= s_axi_rid_next;
s_axi_rdata_reg <= s_axi_rdata_next;
s_axi_rresp_reg <= s_axi_rresp_next;
s_axi_rlast_reg <= s_axi_rlast_next;
s_axi_rvalid_reg <= s_axi_rvalid_next;
m_axil_araddr_reg <= m_axil_araddr_next;
m_axil_arprot_reg <= m_axil_arprot_next;
m_axil_arvalid_reg <= m_axil_arvalid_next;
m_axil_rready_reg <= m_axil_rready_next;
if (rst) begin
state_reg <= STATE_IDLE;
s_axi_arready_reg <= 1'b0;
s_axi_rvalid_reg <= 1'b0;
m_axil_arvalid_reg <= 1'b0;
m_axil_rready_reg <= 1'b0;
end
end
end else begin : downsize
// output is narrower; downsize
// output bus is wider
localparam EXPAND = AXIL_BYTE_LANES > AXI_BYTE_LANES;
localparam DATA_W = EXPAND ? AXIL_DATA_W : AXI_DATA_W;
localparam STRB_W = EXPAND ? AXIL_STRB_W : AXI_STRB_W;
// required number of segments in wider bus
localparam SEG_COUNT = EXPAND ? (AXIL_BYTE_LANES / AXI_BYTE_LANES) : (AXI_BYTE_LANES / AXIL_BYTE_LANES);
// data width and keep width per segment
localparam SEG_DATA_W = DATA_W / SEG_COUNT;
localparam SEG_STRB_W = STRB_W / SEG_COUNT;
localparam [0:0]
STATE_IDLE = 1'd0,
STATE_DATA = 1'd1;
logic [0:0] state_reg = STATE_IDLE, state_next;
logic [AXI_ID_W-1:0] id_reg = '0, id_next;
logic [ADDR_W-1:0] addr_reg = '0, addr_next;
logic [DATA_W-1:0] data_reg = '0, data_next;
logic [1:0] resp_reg = 2'd0, resp_next;
logic [7:0] burst_reg = '0, burst_next;
logic [2:0] burst_size_reg = '0, burst_size_next;
logic [15:0] master_burst_reg = '0, master_burst_next;
logic [2:0] master_burst_size_reg = '0, master_burst_size_next;
logic s_axi_arready_reg = 1'b0, s_axi_arready_next;
logic [AXI_ID_W-1:0] s_axi_rid_reg = '0, s_axi_rid_next;
logic [AXI_DATA_W-1:0] s_axi_rdata_reg = '0, s_axi_rdata_next;
logic [1:0] s_axi_rresp_reg = 2'd0, s_axi_rresp_next;
logic s_axi_rlast_reg = 1'b0, s_axi_rlast_next;
logic s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;
logic [ADDR_W-1:0] m_axil_araddr_reg = '0, m_axil_araddr_next;
logic [2:0] m_axil_arprot_reg = 3'd0, m_axil_arprot_next;
logic m_axil_arvalid_reg = 1'b0, m_axil_arvalid_next;
logic m_axil_rready_reg = 1'b0, m_axil_rready_next;
assign s_axi_rd.arready = s_axi_arready_reg;
assign s_axi_rd.rid = s_axi_rid_reg;
assign s_axi_rd.rdata = s_axi_rdata_reg;
assign s_axi_rd.rresp = s_axi_rresp_reg;
assign s_axi_rd.rlast = s_axi_rlast_reg;
assign s_axi_rd.rvalid = s_axi_rvalid_reg;
assign m_axil_rd.araddr = m_axil_araddr_reg;
assign m_axil_rd.arprot = m_axil_arprot_reg;
assign m_axil_rd.arvalid = m_axil_arvalid_reg;
assign m_axil_rd.rready = m_axil_rready_reg;
always_comb begin
state_next = STATE_IDLE;
id_next = id_reg;
addr_next = addr_reg;
data_next = data_reg;
resp_next = resp_reg;
burst_next = burst_reg;
burst_size_next = burst_size_reg;
master_burst_next = master_burst_reg;
master_burst_size_next = master_burst_size_reg;
s_axi_arready_next = 1'b0;
s_axi_rid_next = s_axi_rid_reg;
s_axi_rdata_next = s_axi_rdata_reg;
s_axi_rresp_next = s_axi_rresp_reg;
s_axi_rlast_next = s_axi_rlast_reg;
s_axi_rvalid_next = s_axi_rvalid_reg && !s_axi_rd.rready;
m_axil_araddr_next = m_axil_araddr_reg;
m_axil_arprot_next = m_axil_arprot_reg;
m_axil_arvalid_next = m_axil_arvalid_reg && !m_axil_rd.arready;
m_axil_rready_next = 1'b0;
// master output is narrower; merge reads and possibly split burst
case (state_reg)
STATE_IDLE: begin
// idle state; wait for new burst
s_axi_arready_next = !m_axil_rd.arvalid;
resp_next = 2'd0;
if (s_axi_rd.arready && s_axi_rd.arvalid) begin
s_axi_arready_next = 1'b0;
id_next = s_axi_rd.arid;
m_axil_araddr_next = s_axi_rd.araddr;
addr_next = s_axi_rd.araddr;
burst_next = s_axi_rd.arlen;
burst_size_next = s_axi_rd.arsize;
if (s_axi_rd.arsize > AXIL_BURST_SIZE) begin
// need to adjust burst size
master_burst_next = 16'({8'd0, s_axi_rd.arlen} << 3'(s_axi_rd.arsize-AXIL_BURST_SIZE)) | 16'(8'(8'(~s_axi_rd.araddr) & 8'(8'hff >> (8-s_axi_rd.arsize))) >> AXIL_BURST_SIZE);
master_burst_size_next = AXIL_BURST_SIZE;
end else begin
// pass through narrow (enough) burst
master_burst_next = 16'(s_axi_rd.arlen);
master_burst_size_next = s_axi_rd.arsize;
end
m_axil_arprot_next = s_axi_rd.arprot;
m_axil_arvalid_next = 1'b1;
m_axil_rready_next = 1'b0;
state_next = STATE_DATA;
end else begin
state_next = STATE_IDLE;
end
end
STATE_DATA: begin
m_axil_rready_next = !s_axi_rd.rvalid && !m_axil_rd.arvalid;
if (m_axil_rd.rready && m_axil_rd.rvalid) begin
data_next[addr_reg[AXI_ADDR_BIT_OFFSET-1:AXIL_ADDR_BIT_OFFSET]*SEG_DATA_W +: SEG_DATA_W] = m_axil_rd.rdata;
if (m_axil_rd.rresp != 0) begin
resp_next = m_axil_rd.rresp;
end
s_axi_rid_next = id_reg;
s_axi_rdata_next = data_next;
s_axi_rresp_next = resp_next;
s_axi_rlast_next = 1'b0;
s_axi_rvalid_next = 1'b0;
master_burst_next = master_burst_reg - 1;
addr_next = (addr_reg + (1 << master_burst_size_reg)) & ({ADDR_W{1'b1}} << master_burst_size_reg);
m_axil_araddr_next = addr_next;
if (addr_next[CL_ADDR_W'(burst_size_reg)] != addr_reg[CL_ADDR_W'(burst_size_reg)]) begin
burst_next = burst_reg - 1;
s_axi_rvalid_next = 1'b1;
end
if (master_burst_reg == 0) begin
if (burst_reg == 0) begin
m_axil_rready_next = 1'b0;
s_axi_rlast_next = 1'b1;
s_axi_rvalid_next = 1'b1;
s_axi_arready_next = !m_axil_rd.arvalid;
state_next = STATE_IDLE;
end else begin
m_axil_arvalid_next = 1'b1;
m_axil_rready_next = 1'b0;
state_next = STATE_DATA;
end
end else begin
m_axil_arvalid_next = 1'b1;
m_axil_rready_next = 1'b0;
state_next = STATE_DATA;
end
end else begin
state_next = STATE_DATA;
end
end
endcase
end
always_ff @(posedge clk) begin
state_reg <= state_next;
id_reg <= id_next;
addr_reg <= addr_next;
data_reg <= data_next;
resp_reg <= resp_next;
burst_reg <= burst_next;
burst_size_reg <= burst_size_next;
master_burst_reg <= master_burst_next;
master_burst_size_reg <= master_burst_size_next;
s_axi_arready_reg <= s_axi_arready_next;
s_axi_rid_reg <= s_axi_rid_next;
s_axi_rdata_reg <= s_axi_rdata_next;
s_axi_rresp_reg <= s_axi_rresp_next;
s_axi_rlast_reg <= s_axi_rlast_next;
s_axi_rvalid_reg <= s_axi_rvalid_next;
m_axil_araddr_reg <= m_axil_araddr_next;
m_axil_arprot_reg <= m_axil_arprot_next;
m_axil_arvalid_reg <= m_axil_arvalid_next;
m_axil_rready_reg <= m_axil_rready_next;
if (rst) begin
state_reg <= STATE_IDLE;
s_axi_arready_reg <= 1'b0;
s_axi_rvalid_reg <= 1'b0;
m_axil_arvalid_reg <= 1'b0;
m_axil_rready_reg <= 1'b0;
end
end
end
endmodule
`resetall

773
src/axi/rtl/taxi_axi_axil_adapter_wr.sv Normal file
View File

@@ -0,0 +1,773 @@
// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2019-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4 to AXI4-Lite adapter (write)
*/
module taxi_axi_axil_adapter_wr #
(
// When adapting to a wider bus, re-pack full-width burst instead of passing through narrow burst if possible
parameter logic CONVERT_BURST = 1'b1,
// When adapting to a wider bus, re-pack all bursts instead of passing through narrow burst if possible
parameter logic CONVERT_NARROW_BURST = 1'b0
)
(
input wire logic clk,
input wire logic rst,
/*
* AXI4 slave interface
*/
taxi_axi_if.wr_slv s_axi_wr,
/*
* AXI4-Lite master interface
*/
taxi_axil_if.wr_mst m_axil_wr
);
// extract parameters
localparam AXI_DATA_W = s_axi_wr.DATA_W;
localparam ADDR_W = s_axi_wr.ADDR_W;
localparam CL_ADDR_W = $clog2(ADDR_W);
localparam AXI_STRB_W = s_axi_wr.STRB_W;
localparam AXI_ID_W = s_axi_wr.ID_W;
localparam logic AWUSER_EN = s_axi_wr.AWUSER_EN && m_axil_wr.AWUSER_EN;
localparam AWUSER_W = s_axi_wr.AWUSER_W;
localparam logic WUSER_EN = s_axi_wr.WUSER_EN && m_axil_wr.WUSER_EN;
localparam WUSER_W = s_axi_wr.WUSER_W;
localparam logic BUSER_EN = s_axi_wr.BUSER_EN && m_axil_wr.BUSER_EN;
localparam BUSER_W = s_axi_wr.BUSER_W;
localparam AXIL_DATA_W = m_axil_wr.DATA_W;
localparam AXIL_STRB_W = m_axil_wr.STRB_W;
localparam AXI_ADDR_BIT_OFFSET = $clog2(AXI_STRB_W);
localparam AXIL_ADDR_BIT_OFFSET = $clog2(AXIL_STRB_W);
localparam AXI_BYTE_LANES = AXI_STRB_W;
localparam AXIL_BYTE_LANES = AXIL_STRB_W;
localparam AXI_BYTE_SIZE = AXI_DATA_W/AXI_BYTE_LANES;
localparam AXIL_BYTE_SIZE = AXIL_DATA_W/AXIL_BYTE_LANES;
localparam logic [2:0] AXI_BURST_SIZE = 3'($clog2(AXI_BYTE_LANES));
localparam logic [2:0] AXIL_BURST_SIZE = 3'($clog2(AXIL_BYTE_LANES));
// check configuration
if (AXI_BYTE_SIZE * AXI_STRB_W != AXI_DATA_W)
$fatal(0, "Error: AXI slave interface data width not evenly divisible (instance %m)");
if (AXIL_BYTE_SIZE * AXIL_STRB_W != AXIL_DATA_W)
$fatal(0, "Error: AXI lite master interface data width not evenly divisible (instance %m)");
if (AXI_BYTE_SIZE != AXIL_BYTE_SIZE)
$fatal(0, "Error: byte size mismatch (instance %m)");
if (2**$clog2(AXI_BYTE_LANES) != AXI_BYTE_LANES)
$fatal(0, "Error: AXI slave interface byte lane count must be even power of two (instance %m)");
if (2**$clog2(AXIL_BYTE_LANES) != AXIL_BYTE_LANES)
$fatal(0, "Error: AXI lite master interface byte lane count must be even power of two (instance %m)");
if (AXIL_BYTE_LANES == AXI_BYTE_LANES) begin : translate
// same width; translate
// output bus is wider
localparam EXPAND = AXIL_BYTE_LANES > AXI_BYTE_LANES;
localparam DATA_W = EXPAND ? AXIL_DATA_W : AXI_DATA_W;
localparam STRB_W = EXPAND ? AXIL_STRB_W : AXI_STRB_W;
// required number of segments in wider bus
localparam SEG_COUNT = EXPAND ? (AXIL_BYTE_LANES / AXI_BYTE_LANES) : (AXI_BYTE_LANES / AXIL_BYTE_LANES);
// data width and keep width per segment
localparam SEG_DATA_W = DATA_W / SEG_COUNT;
localparam SEG_STRB_W = STRB_W / SEG_COUNT;
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_DATA = 2'd1,
STATE_RESP = 2'd2;
logic [1:0] state_reg = STATE_IDLE, state_next;
logic [AXI_ID_W-1:0] id_reg = '0, id_next;
logic [ADDR_W-1:0] addr_reg = '0, addr_next;
logic [DATA_W-1:0] data_reg = '0, data_next;
logic [STRB_W-1:0] strb_reg = '0, strb_next;
logic [7:0] burst_reg = 8'd0, burst_next;
logic [2:0] burst_size_reg = 3'd0, burst_size_next;
logic [2:0] master_burst_size_reg = 3'd0, master_burst_size_next;
logic burst_active_reg = 1'b0, burst_active_next;
logic convert_burst_reg = 1'b0, convert_burst_next;
logic first_transfer_reg = 1'b0, first_transfer_next;
logic last_seg_reg = 1'b0, last_seg_next;
logic s_axi_awready_reg = 1'b0, s_axi_awready_next;
logic s_axi_wready_reg = 1'b0, s_axi_wready_next;
logic [AXI_ID_W-1:0] s_axi_bid_reg = '0, s_axi_bid_next;
logic [1:0] s_axi_bresp_reg = 2'd0, s_axi_bresp_next;
logic s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;
logic [ADDR_W-1:0] m_axil_awaddr_reg = '0, m_axil_awaddr_next;
logic [2:0] m_axil_awprot_reg = 3'd0, m_axil_awprot_next;
logic m_axil_awvalid_reg = 1'b0, m_axil_awvalid_next;
logic [AXIL_DATA_W-1:0] m_axil_wdata_reg = '0, m_axil_wdata_next;
logic [AXIL_STRB_W-1:0] m_axil_wstrb_reg = '0, m_axil_wstrb_next;
logic m_axil_wvalid_reg = 1'b0, m_axil_wvalid_next;
logic m_axil_bready_reg = 1'b0, m_axil_bready_next;
assign s_axi_wr.awready = s_axi_awready_reg;
assign s_axi_wr.wready = s_axi_wready_reg;
assign s_axi_wr.bid = s_axi_bid_reg;
assign s_axi_wr.bresp = s_axi_bresp_reg;
assign s_axi_wr.bvalid = s_axi_bvalid_reg;
assign m_axil_wr.awaddr = m_axil_awaddr_reg;
assign m_axil_wr.awprot = m_axil_awprot_reg;
assign m_axil_wr.awvalid = m_axil_awvalid_reg;
assign m_axil_wr.wdata = m_axil_wdata_reg;
assign m_axil_wr.wstrb = m_axil_wstrb_reg;
assign m_axil_wr.wvalid = m_axil_wvalid_reg;
assign m_axil_wr.bready = m_axil_bready_reg;
always_comb begin
state_next = STATE_IDLE;
id_next = id_reg;
addr_next = addr_reg;
data_next = data_reg;
strb_next = strb_reg;
burst_next = burst_reg;
burst_size_next = burst_size_reg;
master_burst_size_next = master_burst_size_reg;
burst_active_next = burst_active_reg;
convert_burst_next = convert_burst_reg;
first_transfer_next = first_transfer_reg;
last_seg_next = last_seg_reg;
s_axi_awready_next = 1'b0;
s_axi_wready_next = 1'b0;
s_axi_bid_next = s_axi_bid_reg;
s_axi_bresp_next = s_axi_bresp_reg;
s_axi_bvalid_next = s_axi_bvalid_reg && !s_axi_wr.bready;
m_axil_awaddr_next = m_axil_awaddr_reg;
m_axil_awprot_next = m_axil_awprot_reg;
m_axil_awvalid_next = m_axil_awvalid_reg && !m_axil_wr.awready;
m_axil_wdata_next = m_axil_wdata_reg;
m_axil_wstrb_next = m_axil_wstrb_reg;
m_axil_wvalid_next = m_axil_wvalid_reg && !m_axil_wr.wready;
m_axil_bready_next = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state; wait for new burst
s_axi_awready_next = !m_axil_wr.awvalid;
first_transfer_next = 1'b1;
if (s_axi_wr.awready && s_axi_wr.awvalid) begin
s_axi_awready_next = 1'b0;
id_next = s_axi_wr.awid;
m_axil_awaddr_next = s_axi_wr.awaddr;
addr_next = s_axi_wr.awaddr;
burst_next = s_axi_wr.awlen;
burst_size_next = s_axi_wr.awsize;
burst_active_next = 1'b1;
m_axil_awprot_next = s_axi_wr.awprot;
m_axil_awvalid_next = 1'b1;
s_axi_wready_next = !m_axil_wr.wvalid;
state_next = STATE_DATA;
end else begin
state_next = STATE_IDLE;
end
end
STATE_DATA: begin
// data state; transfer write data
s_axi_wready_next = !m_axil_wr.wvalid;
if (s_axi_wr.wready && s_axi_wr.wvalid) begin
m_axil_wdata_next = s_axi_wr.wdata;
m_axil_wstrb_next = s_axi_wr.wstrb;
m_axil_wvalid_next = 1'b1;
burst_next = burst_reg - 1;
burst_active_next = burst_reg != 0;
addr_next = addr_reg + (1 << burst_size_reg);
s_axi_wready_next = 1'b0;
m_axil_bready_next = !s_axi_wr.bvalid && !m_axil_wr.awvalid;
state_next = STATE_RESP;
end else begin
state_next = STATE_DATA;
end
end
STATE_RESP: begin
// resp state; transfer write response
m_axil_bready_next = !s_axi_wr.bvalid && !m_axil_wr.awvalid;
if (m_axil_wr.bready && m_axil_wr.bvalid) begin
m_axil_bready_next = 1'b0;
s_axi_bid_next = id_reg;
first_transfer_next = 1'b0;
if (first_transfer_reg || m_axil_wr.bresp != 0) begin
s_axi_bresp_next = m_axil_wr.bresp;
end
if (burst_active_reg) begin
// burst on slave interface still active; start new AXI lite write
m_axil_awaddr_next = addr_reg;
m_axil_awvalid_next = 1'b1;
s_axi_wready_next = !m_axil_wr.wvalid;
state_next = STATE_DATA;
end else begin
// burst on slave interface finished; return to idle
s_axi_bvalid_next = 1'b1;
s_axi_awready_next = !m_axil_wr.awvalid;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_RESP;
end
end
default: begin
// invalid state
state_next = STATE_IDLE;
end
endcase
end
always_ff @(posedge clk) begin
state_reg <= state_next;
id_reg <= id_next;
addr_reg <= addr_next;
data_reg <= data_next;
strb_reg <= strb_next;
burst_reg <= burst_next;
burst_size_reg <= burst_size_next;
master_burst_size_reg <= master_burst_size_next;
burst_active_reg <= burst_active_next;
convert_burst_reg <= convert_burst_next;
first_transfer_reg <= first_transfer_next;
last_seg_reg <= last_seg_next;
s_axi_awready_reg <= s_axi_awready_next;
s_axi_wready_reg <= s_axi_wready_next;
s_axi_bid_reg <= s_axi_bid_next;
s_axi_bresp_reg <= s_axi_bresp_next;
s_axi_bvalid_reg <= s_axi_bvalid_next;
m_axil_awaddr_reg <= m_axil_awaddr_next;
m_axil_awprot_reg <= m_axil_awprot_next;
m_axil_awvalid_reg <= m_axil_awvalid_next;
m_axil_wdata_reg <= m_axil_wdata_next;
m_axil_wstrb_reg <= m_axil_wstrb_next;
m_axil_wvalid_reg <= m_axil_wvalid_next;
m_axil_bready_reg <= m_axil_bready_next;
if (rst) begin
state_reg <= STATE_IDLE;
s_axi_awready_reg <= 1'b0;
s_axi_wready_reg <= 1'b0;
s_axi_bvalid_reg <= 1'b0;
m_axil_awvalid_reg <= 1'b0;
m_axil_wvalid_reg <= 1'b0;
m_axil_bready_reg <= 1'b0;
end
end
end else if (AXIL_BYTE_LANES > AXI_BYTE_LANES) begin : upsize
// output is wider; upsize
// output bus is wider
localparam EXPAND = AXIL_BYTE_LANES > AXI_BYTE_LANES;
localparam DATA_W = EXPAND ? AXIL_DATA_W : AXI_DATA_W;
localparam STRB_W = EXPAND ? AXIL_STRB_W : AXI_STRB_W;
// required number of segments in wider bus
localparam SEG_COUNT = EXPAND ? (AXIL_BYTE_LANES / AXI_BYTE_LANES) : (AXI_BYTE_LANES / AXIL_BYTE_LANES);
// data width and keep width per segment
localparam SEG_DATA_W = DATA_W / SEG_COUNT;
localparam SEG_STRB_W = STRB_W / SEG_COUNT;
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_DATA = 2'd1,
STATE_DATA_2 = 2'd2,
STATE_RESP = 2'd3;
logic [1:0] state_reg = STATE_IDLE, state_next;
logic [AXI_ID_W-1:0] id_reg = '0, id_next;
logic [ADDR_W-1:0] addr_reg = '0, addr_next;
logic [DATA_W-1:0] data_reg = '0, data_next;
logic [STRB_W-1:0] strb_reg = '0, strb_next;
logic [7:0] burst_reg = 8'd0, burst_next;
logic [2:0] burst_size_reg = 3'd0, burst_size_next;
logic [2:0] master_burst_size_reg = 3'd0, master_burst_size_next;
logic burst_active_reg = 1'b0, burst_active_next;
logic convert_burst_reg = 1'b0, convert_burst_next;
logic first_transfer_reg = 1'b0, first_transfer_next;
logic last_seg_reg = 1'b0, last_seg_next;
logic s_axi_awready_reg = 1'b0, s_axi_awready_next;
logic s_axi_wready_reg = 1'b0, s_axi_wready_next;
logic [AXI_ID_W-1:0] s_axi_bid_reg = '0, s_axi_bid_next;
logic [1:0] s_axi_bresp_reg = 2'd0, s_axi_bresp_next;
logic s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;
logic [ADDR_W-1:0] m_axil_awaddr_reg = '0, m_axil_awaddr_next;
logic [2:0] m_axil_awprot_reg = 3'd0, m_axil_awprot_next;
logic m_axil_awvalid_reg = 1'b0, m_axil_awvalid_next;
logic [AXIL_DATA_W-1:0] m_axil_wdata_reg = '0, m_axil_wdata_next;
logic [AXIL_STRB_W-1:0] m_axil_wstrb_reg = '0, m_axil_wstrb_next;
logic m_axil_wvalid_reg = 1'b0, m_axil_wvalid_next;
logic m_axil_bready_reg = 1'b0, m_axil_bready_next;
assign s_axi_wr.awready = s_axi_awready_reg;
assign s_axi_wr.wready = s_axi_wready_reg;
assign s_axi_wr.bid = s_axi_bid_reg;
assign s_axi_wr.bresp = s_axi_bresp_reg;
assign s_axi_wr.bvalid = s_axi_bvalid_reg;
assign m_axil_wr.awaddr = m_axil_awaddr_reg;
assign m_axil_wr.awprot = m_axil_awprot_reg;
assign m_axil_wr.awvalid = m_axil_awvalid_reg;
assign m_axil_wr.wdata = m_axil_wdata_reg;
assign m_axil_wr.wstrb = m_axil_wstrb_reg;
assign m_axil_wr.wvalid = m_axil_wvalid_reg;
assign m_axil_wr.bready = m_axil_bready_reg;
always_comb begin
state_next = STATE_IDLE;
id_next = id_reg;
addr_next = addr_reg;
data_next = data_reg;
strb_next = strb_reg;
burst_next = burst_reg;
burst_size_next = burst_size_reg;
master_burst_size_next = master_burst_size_reg;
burst_active_next = burst_active_reg;
convert_burst_next = convert_burst_reg;
first_transfer_next = first_transfer_reg;
last_seg_next = last_seg_reg;
s_axi_awready_next = 1'b0;
s_axi_wready_next = 1'b0;
s_axi_bid_next = s_axi_bid_reg;
s_axi_bresp_next = s_axi_bresp_reg;
s_axi_bvalid_next = s_axi_bvalid_reg && !s_axi_wr.bready;
m_axil_awaddr_next = m_axil_awaddr_reg;
m_axil_awprot_next = m_axil_awprot_reg;
m_axil_awvalid_next = m_axil_awvalid_reg && !m_axil_wr.awready;
m_axil_wdata_next = m_axil_wdata_reg;
m_axil_wstrb_next = m_axil_wstrb_reg;
m_axil_wvalid_next = m_axil_wvalid_reg && !m_axil_wr.wready;
m_axil_bready_next = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state; wait for new burst
s_axi_awready_next = !m_axil_wr.awvalid;
first_transfer_next = 1'b1;
strb_next = '0;
if (s_axi_wr.awready && s_axi_wr.awvalid) begin
s_axi_awready_next = 1'b0;
id_next = s_axi_wr.awid;
m_axil_awaddr_next = s_axi_wr.awaddr;
addr_next = s_axi_wr.awaddr;
burst_next = s_axi_wr.awlen;
burst_size_next = s_axi_wr.awsize;
if (CONVERT_BURST && s_axi_wr.awcache[1] && (CONVERT_NARROW_BURST || s_axi_wr.awsize == AXI_BURST_SIZE)) begin
// merge writes
// require CONVERT_BURST and awcache[1] set
convert_burst_next = 1'b1;
master_burst_size_next = AXIL_BURST_SIZE;
state_next = STATE_DATA_2;
end else begin
// output narrow burst
convert_burst_next = 1'b0;
master_burst_size_next = s_axi_wr.awsize;
state_next = STATE_DATA;
end
m_axil_awprot_next = s_axi_wr.awprot;
m_axil_awvalid_next = 1'b1;
s_axi_wready_next = !m_axil_wr.wvalid;
end else begin
state_next = STATE_IDLE;
end
end
STATE_DATA: begin
// data state; transfer write data
s_axi_wready_next = !m_axil_wr.wvalid || m_axil_wr.wready;
if (s_axi_wr.wready && s_axi_wr.wvalid) begin
m_axil_wdata_next = {(AXIL_BYTE_LANES/AXI_BYTE_LANES){s_axi_wr.wdata}};
m_axil_wstrb_next = '0;
m_axil_wstrb_next[addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET] * AXI_STRB_W +: AXI_STRB_W] = s_axi_wr.wstrb;
m_axil_wvalid_next = 1'b1;
burst_next = burst_reg - 1;
burst_active_next = burst_reg != 0;
addr_next = addr_reg + (1 << burst_size_reg);
s_axi_wready_next = 1'b0;
m_axil_bready_next = !s_axi_wr.bvalid && !m_axil_wr.awvalid;
state_next = STATE_RESP;
end else begin
state_next = STATE_DATA;
end
end
STATE_DATA_2: begin
s_axi_wready_next = !m_axil_wr.wvalid;
if (s_axi_wr.wready && s_axi_wr.wvalid) begin
if (CONVERT_NARROW_BURST) begin
for (integer i = 0; i < AXI_BYTE_LANES; i = i + 1) begin
if (s_axi_wr.wstrb[i]) begin
data_next[addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET]*SEG_DATA_W+i*AXIL_BYTE_SIZE +: AXIL_BYTE_SIZE] = s_axi_wr.wdata[i*AXIL_BYTE_SIZE +: AXIL_BYTE_SIZE];
strb_next[addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET]*SEG_STRB_W+i] = 1'b1;
end
end
end else begin
data_next[addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET]*SEG_DATA_W +: SEG_DATA_W] = s_axi_wr.wdata;
strb_next[addr_reg[AXIL_ADDR_BIT_OFFSET-1:AXI_ADDR_BIT_OFFSET]*SEG_STRB_W +: SEG_STRB_W] = s_axi_wr.wstrb;
end
m_axil_wdata_next = data_next;
m_axil_wstrb_next = strb_next;
burst_next = burst_reg - 1;
burst_active_next = burst_reg != 0;
addr_next = addr_reg + (1 << burst_size_reg);
if (burst_reg == 0 || addr_next[CL_ADDR_W'(master_burst_size_reg)] != addr_reg[CL_ADDR_W'(master_burst_size_reg)]) begin
strb_next = '0;
m_axil_wvalid_next = 1'b1;
s_axi_wready_next = 1'b0;
m_axil_bready_next = !s_axi_wr.bvalid && !m_axil_wr.awvalid;
state_next = STATE_RESP;
end else begin
state_next = STATE_DATA_2;
end
end else begin
state_next = STATE_DATA_2;
end
end
STATE_RESP: begin
// resp state; transfer write response
m_axil_bready_next = !s_axi_wr.bvalid && !m_axil_wr.awvalid;
if (m_axil_wr.bready && m_axil_wr.bvalid) begin
m_axil_bready_next = 1'b0;
s_axi_bid_next = id_reg;
first_transfer_next = 1'b0;
if (first_transfer_reg || m_axil_wr.bresp != 0) begin
s_axi_bresp_next = m_axil_wr.bresp;
end
if (burst_active_reg) begin
// burst on slave interface still active; start new AXI lite write
m_axil_awaddr_next = addr_reg;
m_axil_awvalid_next = 1'b1;
s_axi_wready_next = !m_axil_wr.wvalid || m_axil_wr.wready;
if (convert_burst_reg) begin
state_next = STATE_DATA_2;
end else begin
state_next = STATE_DATA;
end
end else begin
// burst on slave interface finished; return to idle
s_axi_bvalid_next = 1'b1;
s_axi_awready_next = !m_axil_wr.awvalid;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_RESP;
end
end
endcase
end
always_ff @(posedge clk) begin
state_reg <= state_next;
id_reg <= id_next;
addr_reg <= addr_next;
data_reg <= data_next;
strb_reg <= strb_next;
burst_reg <= burst_next;
burst_size_reg <= burst_size_next;
master_burst_size_reg <= master_burst_size_next;
burst_active_reg <= burst_active_next;
convert_burst_reg <= convert_burst_next;
first_transfer_reg <= first_transfer_next;
last_seg_reg <= last_seg_next;
s_axi_awready_reg <= s_axi_awready_next;
s_axi_wready_reg <= s_axi_wready_next;
s_axi_bid_reg <= s_axi_bid_next;
s_axi_bresp_reg <= s_axi_bresp_next;
s_axi_bvalid_reg <= s_axi_bvalid_next;
m_axil_awaddr_reg <= m_axil_awaddr_next;
m_axil_awprot_reg <= m_axil_awprot_next;
m_axil_awvalid_reg <= m_axil_awvalid_next;
m_axil_wdata_reg <= m_axil_wdata_next;
m_axil_wstrb_reg <= m_axil_wstrb_next;
m_axil_wvalid_reg <= m_axil_wvalid_next;
m_axil_bready_reg <= m_axil_bready_next;
if (rst) begin
state_reg <= STATE_IDLE;
s_axi_awready_reg <= 1'b0;
s_axi_wready_reg <= 1'b0;
s_axi_bvalid_reg <= 1'b0;
m_axil_awvalid_reg <= 1'b0;
m_axil_wvalid_reg <= 1'b0;
m_axil_bready_reg <= 1'b0;
end
end
end else begin : downsize
// output is narrower; downsize
// output bus is wider
localparam EXPAND = AXIL_BYTE_LANES > AXI_BYTE_LANES;
localparam DATA_W = EXPAND ? AXIL_DATA_W : AXI_DATA_W;
localparam STRB_W = EXPAND ? AXIL_STRB_W : AXI_STRB_W;
// required number of segments in wider bus
localparam SEG_COUNT = EXPAND ? (AXIL_BYTE_LANES / AXI_BYTE_LANES) : (AXI_BYTE_LANES / AXIL_BYTE_LANES);
// data width and keep width per segment
localparam SEG_DATA_W = DATA_W / SEG_COUNT;
localparam SEG_STRB_W = STRB_W / SEG_COUNT;
localparam [1:0]
STATE_IDLE = 2'd0,
STATE_DATA = 2'd1,
STATE_DATA_2 = 2'd2,
STATE_RESP = 2'd3;
logic [1:0] state_reg = STATE_IDLE, state_next;
logic [AXI_ID_W-1:0] id_reg = '0, id_next;
logic [ADDR_W-1:0] addr_reg = '0, addr_next;
logic [DATA_W-1:0] data_reg = '0, data_next;
logic [STRB_W-1:0] strb_reg = '0, strb_next;
logic [7:0] burst_reg = 8'd0, burst_next;
logic [2:0] burst_size_reg = 3'd0, burst_size_next;
logic [2:0] master_burst_size_reg = 3'd0, master_burst_size_next;
logic burst_active_reg = 1'b0, burst_active_next;
logic convert_burst_reg = 1'b0, convert_burst_next;
logic first_transfer_reg = 1'b0, first_transfer_next;
logic last_seg_reg = 1'b0, last_seg_next;
logic s_axi_awready_reg = 1'b0, s_axi_awready_next;
logic s_axi_wready_reg = 1'b0, s_axi_wready_next;
logic [AXI_ID_W-1:0] s_axi_bid_reg = '0, s_axi_bid_next;
logic [1:0] s_axi_bresp_reg = 2'd0, s_axi_bresp_next;
logic s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;
logic [ADDR_W-1:0] m_axil_awaddr_reg = '0, m_axil_awaddr_next;
logic [2:0] m_axil_awprot_reg = 3'd0, m_axil_awprot_next;
logic m_axil_awvalid_reg = 1'b0, m_axil_awvalid_next;
logic [AXIL_DATA_W-1:0] m_axil_wdata_reg = '0, m_axil_wdata_next;
logic [AXIL_STRB_W-1:0] m_axil_wstrb_reg = '0, m_axil_wstrb_next;
logic m_axil_wvalid_reg = 1'b0, m_axil_wvalid_next;
logic m_axil_bready_reg = 1'b0, m_axil_bready_next;
assign s_axi_wr.awready = s_axi_awready_reg;
assign s_axi_wr.wready = s_axi_wready_reg;
assign s_axi_wr.bid = s_axi_bid_reg;
assign s_axi_wr.bresp = s_axi_bresp_reg;
assign s_axi_wr.bvalid = s_axi_bvalid_reg;
assign m_axil_wr.awaddr = m_axil_awaddr_reg;
assign m_axil_wr.awprot = m_axil_awprot_reg;
assign m_axil_wr.awvalid = m_axil_awvalid_reg;
assign m_axil_wr.wdata = m_axil_wdata_reg;
assign m_axil_wr.wstrb = m_axil_wstrb_reg;
assign m_axil_wr.wvalid = m_axil_wvalid_reg;
assign m_axil_wr.bready = m_axil_bready_reg;
always_comb begin
state_next = STATE_IDLE;
id_next = id_reg;
addr_next = addr_reg;
data_next = data_reg;
strb_next = strb_reg;
burst_next = burst_reg;
burst_size_next = burst_size_reg;
master_burst_size_next = master_burst_size_reg;
burst_active_next = burst_active_reg;
convert_burst_next = convert_burst_reg;
first_transfer_next = first_transfer_reg;
last_seg_next = last_seg_reg;
s_axi_awready_next = 1'b0;
s_axi_wready_next = 1'b0;
s_axi_bid_next = s_axi_bid_reg;
s_axi_bresp_next = s_axi_bresp_reg;
s_axi_bvalid_next = s_axi_bvalid_reg && !s_axi_wr.bready;
m_axil_awaddr_next = m_axil_awaddr_reg;
m_axil_awprot_next = m_axil_awprot_reg;
m_axil_awvalid_next = m_axil_awvalid_reg && !m_axil_wr.awready;
m_axil_wdata_next = m_axil_wdata_reg;
m_axil_wstrb_next = m_axil_wstrb_reg;
m_axil_wvalid_next = m_axil_wvalid_reg && !m_axil_wr.wready;
m_axil_bready_next = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state; wait for new burst
s_axi_awready_next = !m_axil_wr.awvalid;
first_transfer_next = 1'b1;
if (s_axi_wr.awready && s_axi_wr.awvalid) begin
s_axi_awready_next = 1'b0;
id_next = s_axi_wr.awid;
m_axil_awaddr_next = s_axi_wr.awaddr;
addr_next = s_axi_wr.awaddr;
burst_next = s_axi_wr.awlen;
burst_size_next = s_axi_wr.awsize;
burst_active_next = 1'b1;
if (s_axi_wr.awsize > AXIL_BURST_SIZE) begin
// need to adjust burst size
master_burst_size_next = AXIL_BURST_SIZE;
end else begin
// pass through narrow (enough) burst
master_burst_size_next = s_axi_wr.awsize;
end
m_axil_awprot_next = s_axi_wr.awprot;
m_axil_awvalid_next = 1'b1;
s_axi_wready_next = !m_axil_wr.wvalid;
state_next = STATE_DATA;
end else begin
state_next = STATE_IDLE;
end
end
STATE_DATA: begin
s_axi_wready_next = !m_axil_wr.wvalid;
if (s_axi_wr.wready && s_axi_wr.wvalid) begin
data_next = s_axi_wr.wdata;
strb_next = s_axi_wr.wstrb;
m_axil_wdata_next = s_axi_wr.wdata[addr_reg[AXI_ADDR_BIT_OFFSET-1:AXIL_ADDR_BIT_OFFSET] * AXIL_DATA_W +: AXIL_DATA_W];
m_axil_wstrb_next = s_axi_wr.wstrb[addr_reg[AXI_ADDR_BIT_OFFSET-1:AXIL_ADDR_BIT_OFFSET] * AXIL_STRB_W +: AXIL_STRB_W];
m_axil_wvalid_next = 1'b1;
burst_next = burst_reg - 1;
burst_active_next = burst_reg != 0;
addr_next = (addr_reg + (1 << master_burst_size_reg)) & ({ADDR_W{1'b1}} << master_burst_size_reg);
last_seg_next = addr_next[CL_ADDR_W'(burst_size_reg)] != addr_reg[CL_ADDR_W'(burst_size_reg)];
s_axi_wready_next = 1'b0;
m_axil_bready_next = !s_axi_wr.bvalid && !m_axil_wr.awvalid;
state_next = STATE_RESP;
end else begin
state_next = STATE_DATA;
end
end
STATE_DATA_2: begin
s_axi_wready_next = 1'b0;
if (!m_axil_wr.wvalid || m_axil_wr.wready) begin
m_axil_wdata_next = data_reg[addr_reg[AXI_ADDR_BIT_OFFSET-1:AXIL_ADDR_BIT_OFFSET] * AXIL_DATA_W +: AXIL_DATA_W];
m_axil_wstrb_next = strb_reg[addr_reg[AXI_ADDR_BIT_OFFSET-1:AXIL_ADDR_BIT_OFFSET] * AXIL_STRB_W +: AXIL_STRB_W];
m_axil_wvalid_next = 1'b1;
addr_next = (addr_reg + (1 << master_burst_size_reg)) & ({ADDR_W{1'b1}} << master_burst_size_reg);
last_seg_next = addr_next[CL_ADDR_W'(burst_size_reg)] != addr_reg[CL_ADDR_W'(burst_size_reg)];
s_axi_wready_next = 1'b0;
m_axil_bready_next = !s_axi_wr.bvalid && !m_axil_wr.awvalid;
state_next = STATE_RESP;
end else begin
state_next = STATE_DATA_2;
end
end
STATE_RESP: begin
// resp state; transfer write response
m_axil_bready_next = !s_axi_wr.bvalid && !m_axil_wr.awvalid;
if (m_axil_wr.bready && m_axil_wr.bvalid) begin
first_transfer_next = 1'b0;
m_axil_awaddr_next = addr_reg;
m_axil_bready_next = 1'b0;
s_axi_bid_next = id_reg;
if (first_transfer_reg || m_axil_wr.bresp != 0) begin
s_axi_bresp_next = m_axil_wr.bresp;
end
if (burst_active_reg || !last_seg_reg) begin
// burst on slave interface still active; start new burst
m_axil_awvalid_next = 1'b1;
if (last_seg_reg) begin
s_axi_wready_next = !m_axil_wr.wvalid;
state_next = STATE_DATA;
end else begin
s_axi_wready_next = 1'b0;
state_next = STATE_DATA_2;
end
end else begin
// burst on slave interface finished; return to idle
s_axi_bvalid_next = 1'b1;
s_axi_awready_next = !m_axil_wr.awvalid;
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_RESP;
end
end
endcase
end
always_ff @(posedge clk) begin
state_reg <= state_next;
id_reg <= id_next;
addr_reg <= addr_next;
data_reg <= data_next;
strb_reg <= strb_next;
burst_reg <= burst_next;
burst_size_reg <= burst_size_next;
master_burst_size_reg <= master_burst_size_next;
burst_active_reg <= burst_active_next;
convert_burst_reg <= convert_burst_next;
first_transfer_reg <= first_transfer_next;
last_seg_reg <= last_seg_next;
s_axi_awready_reg <= s_axi_awready_next;
s_axi_wready_reg <= s_axi_wready_next;
s_axi_bid_reg <= s_axi_bid_next;
s_axi_bresp_reg <= s_axi_bresp_next;
s_axi_bvalid_reg <= s_axi_bvalid_next;
m_axil_awaddr_reg <= m_axil_awaddr_next;
m_axil_awprot_reg <= m_axil_awprot_next;
m_axil_awvalid_reg <= m_axil_awvalid_next;
m_axil_wdata_reg <= m_axil_wdata_next;
m_axil_wstrb_reg <= m_axil_wstrb_next;
m_axil_wvalid_reg <= m_axil_wvalid_next;
m_axil_bready_reg <= m_axil_bready_next;
if (rst) begin
state_reg <= STATE_IDLE;
s_axi_awready_reg <= 1'b0;
s_axi_wready_reg <= 1'b0;
s_axi_bvalid_reg <= 1'b0;
m_axil_awvalid_reg <= 1'b0;
m_axil_wvalid_reg <= 1'b0;
m_axil_bready_reg <= 1'b0;
end
end
end
endmodule
`resetall

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src/axi/tb/taxi_axi_axil_adapter/Makefile Normal file
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# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2020-2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
TOPLEVEL_LANG = verilog
SIM ?= verilator
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
RTL_DIR = ../../rtl
LIB_DIR = ../../lib
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
DUT = taxi_axi_axil_adapter
COCOTB_TEST_MODULES = test_$(DUT)
COCOTB_TOPLEVEL = test_$(DUT)
MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).f
# handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_ADDR_W := 32
export PARAM_AXI_DATA_W := 32
export PARAM_AXI_STRB_W := $(shell expr $(PARAM_AXI_DATA_W) / 8 )
export PARAM_AXI_ID_W := 8
export PARAM_AXIL_DATA_W := 32
export PARAM_AXIL_STRB_W := $(shell expr $(PARAM_AXIL_DATA_W) / 8 )
export PARAM_AWUSER_EN := 0
export PARAM_AWUSER_W := 1
export PARAM_WUSER_EN := 0
export PARAM_WUSER_W := 1
export PARAM_BUSER_EN := 0
export PARAM_BUSER_W := 1
export PARAM_ARUSER_EN := 0
export PARAM_ARUSER_W := 1
export PARAM_RUSER_EN := 0
export PARAM_RUSER_W := 1
export PARAM_CONVERT_BURST := 1
export PARAM_CONVERT_NARROW_BURST := 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-WIDTH
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
VERILATOR_TRACE = 1
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim

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src/axi/tb/taxi_axi_axil_adapter/test_taxi_axi_axil_adapter.py Normal file
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#!/usr/bin/env python
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""
Copyright (c) 2020-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import itertools
import logging
import os
import random
import cocotb_test.simulator
import pytest
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer
from cocotb.regression import TestFactory
from cocotbext.axi import AxiBus, AxiLiteBus, AxiMaster, AxiLiteRam
class TB(object):
def __init__(self, dut):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
self.axi_master = AxiMaster(AxiBus.from_entity(dut.s_axi), dut.clk, dut.rst)
self.axil_ram = AxiLiteRam(AxiLiteBus.from_entity(dut.m_axil), dut.clk, dut.rst, size=2**16)
def set_idle_generator(self, generator=None):
if generator:
self.axi_master.write_if.aw_channel.set_pause_generator(generator())
self.axi_master.write_if.w_channel.set_pause_generator(generator())
self.axi_master.read_if.ar_channel.set_pause_generator(generator())
self.axil_ram.write_if.b_channel.set_pause_generator(generator())
self.axil_ram.read_if.r_channel.set_pause_generator(generator())
def set_backpressure_generator(self, generator=None):
if generator:
self.axi_master.write_if.b_channel.set_pause_generator(generator())
self.axi_master.read_if.r_channel.set_pause_generator(generator())
self.axil_ram.write_if.aw_channel.set_pause_generator(generator())
self.axil_ram.write_if.w_channel.set_pause_generator(generator())
self.axil_ram.read_if.ar_channel.set_pause_generator(generator())
async def cycle_reset(self):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, size=None):
tb = TB(dut)
byte_lanes = tb.axi_master.write_if.byte_lanes
max_burst_size = (byte_lanes-1).bit_length()
if size is None:
size = max_burst_size
await tb.cycle_reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in list(range(1, byte_lanes*2))+[1024]:
for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
tb.log.info("length %d, offset %d, size %d", length, offset, size)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
tb.axil_ram.write(addr-128, b'\xaa'*(length+256))
await tb.axi_master.write(addr, test_data, size=size)
tb.log.debug("%s", tb.axil_ram.hexdump_str((addr & ~0xf)-16, (((addr & 0xf)+length-1) & ~0xf)+48))
assert tb.axil_ram.read(addr, length) == test_data
assert tb.axil_ram.read(addr-1, 1) == b'\xaa'
assert tb.axil_ram.read(addr+length, 1) == b'\xaa'
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None, size=None):
tb = TB(dut)
byte_lanes = tb.axi_master.write_if.byte_lanes
max_burst_size = (byte_lanes-1).bit_length()
if size is None:
size = max_burst_size
await tb.cycle_reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in list(range(1, byte_lanes*2))+[1024]:
for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
tb.log.info("length %d, offset %d, size %d", length, offset, size)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
tb.axil_ram.write(addr, test_data)
data = await tb.axi_master.read(addr, length, size=size)
assert data.data == test_data
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
tb = TB(dut)
await tb.cycle_reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
async def worker(master, offset, aperture, count=16):
for k in range(count):
length = random.randint(1, min(512, aperture))
addr = offset+random.randint(0, aperture-length)
test_data = bytearray([x % 256 for x in range(length)])
await Timer(random.randint(1, 100), 'ns')
await master.write(addr, test_data)
await Timer(random.randint(1, 100), 'ns')
data = await master.read(addr, length)
assert data.data == test_data
workers = []
for k in range(16):
workers.append(cocotb.start_soon(worker(tb.axi_master, k*0x1000, 0x1000, count=16)))
while workers:
await workers.pop(0).join()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
def cycle_pause():
return itertools.cycle([1, 1, 1, 0])
if cocotb.SIM_NAME:
data_width = len(cocotb.top.s_axi.wdata)
byte_lanes = data_width // 8
max_burst_size = (byte_lanes-1).bit_length()
for test in [run_test_write, run_test_read]:
factory = TestFactory(test)
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.add_option("size", [None]+list(range(max_burst_size)))
factory.generate_tests()
factory = TestFactory(run_stress_test)
factory.add_option("idle_inserter", [None, cycle_pause])
factory.add_option("backpressure_inserter", [None, cycle_pause])
factory.generate_tests()
# cocotb-test
tests_dir = os.path.abspath(os.path.dirname(__file__))
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
def process_f_files(files):
lst = {}
for f in files:
if f[-2:].lower() == '.f':
with open(f, 'r') as fp:
l = fp.read().split()
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
lst[os.path.basename(f)] = f
else:
lst[os.path.basename(f)] = f
return list(lst.values())
@pytest.mark.parametrize("axil_data_w", [8, 16, 32])
@pytest.mark.parametrize("axi_data_w", [8, 16, 32])
def test_taxi_axi_axil_adapter(request, axi_data_w, axil_data_w):
dut = "taxi_axi_axil_adapter"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = module
verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.sv"),
os.path.join(rtl_dir, f"{dut}.f"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
parameters['ADDR_W'] = 32
parameters['AXI_DATA_W'] = axi_data_w
parameters['AXI_STRB_W'] = parameters['AXI_DATA_W'] // 8
parameters['AXI_ID_W'] = 8
parameters['AXIL_DATA_W'] = axil_data_w
parameters['AXIL_STRB_W'] = parameters['AXIL_DATA_W'] // 8
parameters['AWUSER_EN'] = 0
parameters['AWUSER_W'] = 1
parameters['WUSER_EN'] = 0
parameters['WUSER_W'] = 1
parameters['BUSER_EN'] = 0
parameters['BUSER_W'] = 1
parameters['ARUSER_EN'] = 0
parameters['ARUSER_W'] = 1
parameters['RUSER_EN'] = 0
parameters['RUSER_W'] = 1
parameters['CONVERT_BURST'] = 1
parameters['CONVERT_NARROW_BURST'] = 1
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
simulator="verilator",
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)

102
src/axi/tb/taxi_axi_axil_adapter/test_taxi_axi_axil_adapter.sv Normal file
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// SPDX-License-Identifier: CERN-OHL-S-2.0
/*
Copyright (c) 2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
*/
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* AXI4 to AXI4-Lite adapter testbench
*/
module test_taxi_axi_axil_adapter #
(
/* verilator lint_off WIDTHTRUNC */
parameter ADDR_W = 32,
parameter AXI_DATA_W = 32,
parameter AXI_STRB_W = (AXI_DATA_W/8),
parameter AXI_ID_W = 8,
parameter AXIL_DATA_W = 32,
parameter AXIL_STRB_W = (AXIL_DATA_W/8),
parameter logic AWUSER_EN = 1'b0,
parameter AWUSER_W = 1,
parameter logic WUSER_EN = 1'b0,
parameter WUSER_W = 1,
parameter logic BUSER_EN = 1'b0,
parameter BUSER_W = 1,
parameter logic ARUSER_EN = 1'b0,
parameter ARUSER_W = 1,
parameter logic RUSER_EN = 1'b0,
parameter RUSER_W = 1,
parameter logic CONVERT_BURST = 1'b1,
parameter logic CONVERT_NARROW_BURST = 1'b0
/* verilator lint_on WIDTHTRUNC */
)
();
logic clk;
logic rst;
taxi_axi_if #(
.DATA_W(AXI_DATA_W),
.ADDR_W(ADDR_W),
.STRB_W(AXI_STRB_W),
.ID_W(AXI_ID_W),
.AWUSER_EN(AWUSER_EN),
.AWUSER_W(AWUSER_W),
.WUSER_EN(WUSER_EN),
.WUSER_W(WUSER_W),
.BUSER_EN(BUSER_EN),
.BUSER_W(BUSER_W),
.ARUSER_EN(ARUSER_EN),
.ARUSER_W(ARUSER_W),
.RUSER_EN(RUSER_EN),
.RUSER_W(RUSER_W)
) s_axi();
taxi_axil_if #(
.DATA_W(AXIL_DATA_W),
.ADDR_W(ADDR_W),
.STRB_W(AXIL_STRB_W),
.AWUSER_EN(AWUSER_EN),
.AWUSER_W(AWUSER_W),
.WUSER_EN(WUSER_EN),
.WUSER_W(WUSER_W),
.BUSER_EN(BUSER_EN),
.BUSER_W(BUSER_W),
.ARUSER_EN(ARUSER_EN),
.ARUSER_W(ARUSER_W),
.RUSER_EN(RUSER_EN),
.RUSER_W(RUSER_W)
) m_axil();
taxi_axi_axil_adapter #(
.CONVERT_BURST(CONVERT_BURST),
.CONVERT_NARROW_BURST(CONVERT_NARROW_BURST)
)
uut (
.clk(clk),
.rst(rst),
/*
* AXI4 slave interface
*/
.s_axi_wr(s_axi),
.s_axi_rd(s_axi),
/*
* AXI4-Lite master interface
*/
.m_axil_wr(m_axil),
.m_axil_rd(m_axil)
);
endmodule
`resetall