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axi: Add AXI lite RAM module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
@@ -28,6 +28,7 @@ To facilitate the dual-license model, contributions to the project can only be a
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* AXI lite
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* SV interface for AXI lite
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* Register slice
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* Single port RAM
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* AXI stream
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* SV interface for AXI stream
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* Register slice
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165
rtl/axi/taxi_axil_ram.sv
Normal file
165
rtl/axi/taxi_axil_ram.sv
Normal file
@@ -0,0 +1,165 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2018-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4-Lite RAM
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*/
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module taxi_axil_ram #
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(
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// Width of address bus in bits
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parameter ADDR_W = 16,
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// Extra pipeline register on output
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parameter logic PIPELINE_OUTPUT = 1'b0
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* AXI4-Lite slave interface
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*/
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taxi_axil_if.wr_slv s_axil_wr,
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taxi_axil_if.rd_slv s_axil_rd
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);
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// extract parameters
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localparam DATA_W = s_axil_wr.DATA_W;
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localparam STRB_W = s_axil_wr.STRB_W;
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localparam VALID_ADDR_W = ADDR_W - $clog2(STRB_W);
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localparam BYTE_LANES = STRB_W;
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localparam BYTE_W = DATA_W/BYTE_LANES;
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// check configuration
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if (BYTE_W * STRB_W != DATA_W)
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$fatal(0, "Error: AXI data width not evenly divisible (instance %m)");
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if (2**$clog2(BYTE_LANES) != BYTE_LANES)
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$fatal(0, "Error: AXI byte lane count must be even power of two (instance %m)");
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if (s_axil_wr.DATA_W != s_axil_rd.DATA_W)
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$fatal(0, "Error: AXI interface configuration mismatch (instance %m)");
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if (s_axil_wr.ADDR_W < ADDR_W || s_axil_rd.ADDR_W < ADDR_W)
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$fatal(0, "Error: AXI address width is insufficient (instance %m)");
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reg mem_wr_en;
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reg mem_rd_en;
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reg s_axil_awready_reg = 1'b0, s_axil_awready_next;
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reg s_axil_wready_reg = 1'b0, s_axil_wready_next;
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reg s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next;
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reg s_axil_arready_reg = 1'b0, s_axil_arready_next;
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reg [DATA_W-1:0] s_axil_rdata_reg = '0, s_axil_rdata_next;
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reg s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next;
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reg [DATA_W-1:0] s_axil_rdata_pipe_reg = '0;
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reg s_axil_rvalid_pipe_reg = 1'b0;
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// (* RAM_STYLE="BLOCK" *)
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reg [DATA_W-1:0] mem[(2**VALID_ADDR_W)-1:0];
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wire [VALID_ADDR_W-1:0] s_axil_awaddr_valid = VALID_ADDR_W'(s_axil_wr.awaddr >> (ADDR_W - VALID_ADDR_W));
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wire [VALID_ADDR_W-1:0] s_axil_araddr_valid = VALID_ADDR_W'(s_axil_rd.araddr >> (ADDR_W - VALID_ADDR_W));
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assign s_axil_wr.awready = s_axil_awready_reg;
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assign s_axil_wr.wready = s_axil_wready_reg;
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assign s_axil_wr.bresp = 2'b00;
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assign s_axil_wr.bvalid = s_axil_bvalid_reg;
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assign s_axil_rd.arready = s_axil_arready_reg;
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assign s_axil_rd.rdata = PIPELINE_OUTPUT ? s_axil_rdata_pipe_reg : s_axil_rdata_reg;
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assign s_axil_rd.rresp = 2'b00;
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assign s_axil_rd.rvalid = PIPELINE_OUTPUT ? s_axil_rvalid_pipe_reg : s_axil_rvalid_reg;
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initial begin
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// two nested loops for smaller number of iterations per loop
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// workaround for synthesizer complaints about large loop counts
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for (integer i = 0; i < 2**VALID_ADDR_W; i = i + 2**(VALID_ADDR_W/2)) begin
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for (integer j = i; j < i + 2**(VALID_ADDR_W/2); j = j + 1) begin
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mem[j] = '0;
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end
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end
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end
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always_comb begin
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mem_wr_en = 1'b0;
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s_axil_awready_next = 1'b0;
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s_axil_wready_next = 1'b0;
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s_axil_bvalid_next = s_axil_bvalid_reg && !s_axil_wr.bready;
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if (s_axil_wr.awvalid && s_axil_wr.wvalid && (!s_axil_wr.bvalid || s_axil_wr.bready) && (!s_axil_wr.awready && !s_axil_wr.wready)) begin
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s_axil_awready_next = 1'b1;
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s_axil_wready_next = 1'b1;
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s_axil_bvalid_next = 1'b1;
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mem_wr_en = 1'b1;
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end
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end
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always_ff @(posedge clk) begin
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s_axil_awready_reg <= s_axil_awready_next;
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s_axil_wready_reg <= s_axil_wready_next;
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s_axil_bvalid_reg <= s_axil_bvalid_next;
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for (integer i = 0; i < BYTE_LANES; i = i + 1) begin
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if (mem_wr_en && s_axil_wr.wstrb[i]) begin
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mem[s_axil_awaddr_valid][BYTE_W*i +: BYTE_W] <= s_axil_wr.wdata[BYTE_W*i +: BYTE_W];
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end
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end
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if (rst) begin
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s_axil_awready_reg <= 1'b0;
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s_axil_wready_reg <= 1'b0;
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s_axil_bvalid_reg <= 1'b0;
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end
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end
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always_comb begin
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mem_rd_en = 1'b0;
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s_axil_arready_next = 1'b0;
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s_axil_rvalid_next = s_axil_rvalid_reg && !(s_axil_rd.rready || (PIPELINE_OUTPUT && !s_axil_rvalid_pipe_reg));
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if (s_axil_rd.arvalid && (!s_axil_rd.rvalid || s_axil_rd.rready || (PIPELINE_OUTPUT && !s_axil_rvalid_pipe_reg)) && (!s_axil_rd.arready)) begin
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s_axil_arready_next = 1'b1;
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s_axil_rvalid_next = 1'b1;
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mem_rd_en = 1'b1;
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end
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end
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always_ff @(posedge clk) begin
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s_axil_arready_reg <= s_axil_arready_next;
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s_axil_rvalid_reg <= s_axil_rvalid_next;
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if (mem_rd_en) begin
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s_axil_rdata_reg <= mem[s_axil_araddr_valid];
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end
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if (!s_axil_rvalid_pipe_reg || s_axil_rd.rready) begin
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s_axil_rdata_pipe_reg <= s_axil_rdata_reg;
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s_axil_rvalid_pipe_reg <= s_axil_rvalid_reg;
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end
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if (rst) begin
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s_axil_arready_reg <= 1'b0;
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s_axil_rvalid_reg <= 1'b0;
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s_axil_rvalid_pipe_reg <= 1'b0;
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end
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end
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endmodule
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`resetall
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49
tb/axi/taxi_axil_ram/Makefile
Normal file
49
tb/axi/taxi_axil_ram/Makefile
Normal file
@@ -0,0 +1,49 @@
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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#
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# Copyright (c) 2020-2025 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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TOPLEVEL_LANG = verilog
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SIM ?= verilator
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WAVES ?= 0
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COCOTB_HDL_TIMEUNIT = 1ns
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COCOTB_HDL_TIMEPRECISION = 1ps
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DUT = taxi_axil_ram
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COCOTB_TEST_MODULES = test_$(DUT)
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COCOTB_TOPLEVEL = test_$(DUT)
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MODULE = $(COCOTB_TEST_MODULES)
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TOPLEVEL = $(COCOTB_TOPLEVEL)
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VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
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VERILOG_SOURCES += ../../../rtl/axi/$(DUT).sv
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VERILOG_SOURCES += ../../../rtl/axi/taxi_axil_if.sv
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# handle file list files
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process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
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process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
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uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
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VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
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# module parameters
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export PARAM_DATA_W := 32
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export PARAM_ADDR_W := 16
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export PARAM_PIPELINE_OUTPUT := 0
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
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else ifeq ($(SIM), verilator)
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
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ifeq ($(WAVES), 1)
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COMPILE_ARGS += --trace-fst
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VERILATOR_TRACE = 1
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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221
tb/axi/taxi_axil_ram/test_taxi_axil_ram.py
Normal file
221
tb/axi/taxi_axil_ram/test_taxi_axil_ram.py
Normal file
@@ -0,0 +1,221 @@
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#!/usr/bin/env python
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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"""
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Copyright (c) 2020-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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"""
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import itertools
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import logging
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import os
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import random
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import cocotb_test.simulator
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import pytest
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge, Timer
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from cocotb.regression import TestFactory
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from cocotbext.axi import AxiLiteBus, AxiLiteMaster
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class TB(object):
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def __init__(self, dut):
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self.dut = dut
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self.log = logging.getLogger("cocotb.tb")
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self.log.setLevel(logging.DEBUG)
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cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
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self.axil_master = AxiLiteMaster(AxiLiteBus.from_entity(dut.s_axil), dut.clk, dut.rst)
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def set_idle_generator(self, generator=None):
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if generator:
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self.axil_master.write_if.aw_channel.set_pause_generator(generator())
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self.axil_master.write_if.w_channel.set_pause_generator(generator())
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self.axil_master.read_if.ar_channel.set_pause_generator(generator())
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def set_backpressure_generator(self, generator=None):
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if generator:
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self.axil_master.write_if.b_channel.set_pause_generator(generator())
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self.axil_master.read_if.r_channel.set_pause_generator(generator())
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async def cycle_reset(self):
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self.dut.rst.setimmediatevalue(0)
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 1
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 0
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_inserter=None):
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tb = TB(dut)
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byte_lanes = tb.axil_master.write_if.byte_lanes
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await tb.cycle_reset()
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tb.set_idle_generator(idle_inserter)
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tb.set_backpressure_generator(backpressure_inserter)
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for length in range(1, byte_lanes*2):
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for offset in range(byte_lanes):
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tb.log.info("length %d, offset %d", length, offset)
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addr = offset+0x1000
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test_data = bytearray([x % 256 for x in range(length)])
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await tb.axil_master.write(addr-4, b'\xaa'*(length+8))
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await tb.axil_master.write(addr, test_data)
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data = await tb.axil_master.read(addr-1, length+2)
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assert data.data == b'\xaa'+test_data+b'\xaa'
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inserter=None):
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tb = TB(dut)
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byte_lanes = tb.axil_master.write_if.byte_lanes
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await tb.cycle_reset()
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tb.set_idle_generator(idle_inserter)
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tb.set_backpressure_generator(backpressure_inserter)
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for length in range(1, byte_lanes*2):
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for offset in range(byte_lanes):
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tb.log.info("length %d, offset %d", length, offset)
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addr = offset+0x1000
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test_data = bytearray([x % 256 for x in range(length)])
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await tb.axil_master.write(addr, test_data)
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data = await tb.axil_master.read(addr, length)
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assert data.data == test_data
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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async def run_stress_test(dut, idle_inserter=None, backpressure_inserter=None):
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tb = TB(dut)
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await tb.cycle_reset()
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tb.set_idle_generator(idle_inserter)
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tb.set_backpressure_generator(backpressure_inserter)
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async def worker(master, offset, aperture, count=16):
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for k in range(count):
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length = random.randint(1, min(32, aperture))
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addr = offset+random.randint(0, aperture-length)
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test_data = bytearray([x % 256 for x in range(length)])
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await Timer(random.randint(1, 100), 'ns')
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await master.write(addr, test_data)
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await Timer(random.randint(1, 100), 'ns')
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data = await master.read(addr, length)
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assert data.data == test_data
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workers = []
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for k in range(16):
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workers.append(cocotb.start_soon(worker(tb.axil_master, k*0x1000, 0x1000, count=16)))
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while workers:
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await workers.pop(0).join()
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await RisingEdge(dut.clk)
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await RisingEdge(dut.clk)
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def cycle_pause():
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return itertools.cycle([1, 1, 1, 0])
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if cocotb.SIM_NAME:
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for test in [run_test_write, run_test_read, run_stress_test]:
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factory = TestFactory(test)
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factory.add_option("idle_inserter", [None, cycle_pause])
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factory.add_option("backpressure_inserter", [None, cycle_pause])
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factory.generate_tests()
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# cocotb-test
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tests_dir = os.path.abspath(os.path.dirname(__file__))
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rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
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def process_f_files(files):
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lst = {}
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for f in files:
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if f[-2:].lower() == '.f':
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with open(f, 'r') as fp:
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l = fp.read().split()
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for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
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lst[os.path.basename(f)] = f
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else:
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lst[os.path.basename(f)] = f
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return list(lst.values())
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@pytest.mark.parametrize("data_w", [8, 16, 32])
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def test_taxi_axil_ram(request, data_w):
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dut = "taxi_axil_ram"
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module = os.path.splitext(os.path.basename(__file__))[0]
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toplevel = module
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verilog_sources = [
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os.path.join(tests_dir, f"{toplevel}.sv"),
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os.path.join(rtl_dir, "axi", f"{dut}.sv"),
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os.path.join(rtl_dir, "axi", "taxi_axil_if.sv"),
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]
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verilog_sources = process_f_files(verilog_sources)
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parameters = {}
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parameters['DATA_W'] = data_w
|
||||
parameters['ADDR_W'] = 16
|
||||
parameters['PIPELINE_OUTPUT'] = 0
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
53
tb/axi/taxi_axil_ram/test_taxi_axil_ram.sv
Normal file
53
tb/axi/taxi_axil_ram/test_taxi_axil_ram.sv
Normal file
@@ -0,0 +1,53 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* AXI4 lite RAM testbench
|
||||
*/
|
||||
module test_taxi_axil_ram #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter DATA_W = 32,
|
||||
parameter ADDR_W = 16,
|
||||
parameter PIPELINE_OUTPUT = 0
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axil_if #(
|
||||
.DATA_W(DATA_W),
|
||||
.ADDR_W(ADDR_W+16)
|
||||
) s_axil(), m_axil();
|
||||
|
||||
taxi_axil_ram #(
|
||||
.ADDR_W(ADDR_W),
|
||||
.PIPELINE_OUTPUT(PIPELINE_OUTPUT)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI4-Lite slave interface
|
||||
*/
|
||||
.s_axil_wr(s_axil),
|
||||
.s_axil_rd(s_axil)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user