axi: Add AXI lite RAM module and testbench

Signed-off-by: Alex Forencich <alex@alexforencich.com>
2026-05-24 16:30:58 -07:00 · 2025-02-27 00:26:03 -08:00
parent c478f187b1
commit 0632b1982e
5 changed files with 489 additions and 0 deletions
--- a/README.md
+++ b/README.md
@@ -28,6 +28,7 @@ To facilitate the dual-license model, contributions to the project can only be a
 *  AXI lite
    *  SV interface for AXI lite
    *  Register slice
+    *  Single port RAM
 *  AXI stream
    *  SV interface for AXI stream
    *  Register slice