eth: Update VCU118 example design to use 32-bit MACs at 10G

Signed-off-by: Alex Forencich <alex@alexforencich.com>

src/eth/example/VCU118/fpga/fpga/Makefile

@@ -39,6 +39,9 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
 IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl
 IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl
 
+# Configuration
+CONFIG_TCL_FILES = ./config.tcl
+
 include ../common/vivado.mk
 
 program: $(PROJECT).bit
@@ -88,4 +91,3 @@ flash: $(PROJECT)_primary.mcs $(PROJECT)_secondary.mcs $(PROJECT)_primary.prm $(
 	echo "boot_hw_device [current_hw_device]" >> flash.tcl
 	echo "exit" >> flash.tcl
 	vivado -nojournal -nolog -mode batch -source flash.tcl
-

src/eth/example/VCU118/fpga/fpga/config.tcl

@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+set params [dict create]
+
+# 10G MAC configuration
+dict set params CFG_LOW_LATENCY "1"
+dict set params COMBINED_MAC_PCS "1"
+dict set params MAC_DATA_W "64"
+
+# apply parameters to top-level
+set param_list {}
+dict for {name value} $params {
+    lappend param_list $name=$value
+}
+
+set_property generic $param_list [get_filesets sources_1]

src/eth/example/VCU118/fpga/fpga_10g/Makefile

@@ -37,7 +37,10 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
 
 # IP
 IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl
-IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_10g_156.tcl
+IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_156.tcl
+
+# Configuration
+CONFIG_TCL_FILES = ./config.tcl
 
 include ../common/vivado.mk
 
@@ -88,4 +91,3 @@ flash: $(PROJECT)_primary.mcs $(PROJECT)_secondary.mcs $(PROJECT)_primary.prm $(
 	echo "boot_hw_device [current_hw_device]" >> flash.tcl
 	echo "exit" >> flash.tcl
 	vivado -nojournal -nolog -mode batch -source flash.tcl
-

src/eth/example/VCU118/fpga/fpga_10g/config.tcl

@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+set params [dict create]
+
+# 10G MAC configuration
+dict set params CFG_LOW_LATENCY "1"
+dict set params COMBINED_MAC_PCS "1"
+dict set params MAC_DATA_W "32"
+
+# apply parameters to top-level
+set param_list {}
+dict for {name value} $params {
+    lappend param_list $name=$value
+}
+
+set_property generic $param_list [get_filesets sources_1]

src/eth/example/VCU118/fpga/rtl/fpga.sv

@@ -17,9 +17,16 @@ Authors:
  */
 module fpga #
 (
+    // simulation (set to avoid vendor primitives)
     parameter logic SIM = 1'b0,
+    // vendor ("GENERIC", "XILINX", "ALTERA")
     parameter string VENDOR = "XILINX",
-    parameter string FAMILY = "virtexuplus"
+    // device family
+    parameter string FAMILY = "virtexuplus",
+    // 10G/25G MAC configuration
+    parameter logic CFG_LOW_LATENCY = 1'b1,
+    parameter logic COMBINED_MAC_PCS = 1'b1,
+    parameter MAC_DATA_W = 64
 )
 (
     /*
@@ -120,12 +127,12 @@ wire mmcm_clkfb;
 
 IBUFGDS #(
    .DIFF_TERM("FALSE"),
-   .IBUF_LOW_PWR("FALSE")   
+   .IBUF_LOW_PWR("FALSE")
 )
 clk_125mhz_ibufg_inst (
    .O   (clk_125mhz_ibufg),
    .I   (clk_125mhz_p),
-   .IB  (clk_125mhz_n) 
+   .IB  (clk_125mhz_n)
 );
 
 // MMCM instance
@@ -325,7 +332,7 @@ assign pcspma_an_config_vector[5]     = 1'b0;    // full duplex - SGMII reserved
 assign pcspma_an_config_vector[4:1]   = 4'b0000; // reserved
 assign pcspma_an_config_vector[0]     = 1'b1;    // SGMII
 
-sgmii_pcs_pma_0 
+sgmii_pcs_pma_0
 eth_pcspma (
     // SGMII
     .txp_0                  (phy_sgmii_tx_p),
@@ -355,7 +362,7 @@ eth_pcspma (
     .sgmii_clk_r_0          (),
     .sgmii_clk_f_0          (),
     .sgmii_clk_en_0         (phy_gmii_clk_en_int),
-    
+
     // Speed control
     .speed_is_10_100_0      (pcspma_status_speed != 2'b10),
     .speed_is_100_0         (pcspma_status_speed == 2'b01),
@@ -440,7 +447,10 @@ assign led = sw[3] ? (sw[0] ? pcspma_status_vector[15:8] : pcspma_status_vector[
 fpga_core #(
     .SIM(SIM),
     .VENDOR(VENDOR),
-    .FAMILY(FAMILY)
+    .FAMILY(FAMILY),
+    .CFG_LOW_LATENCY(CFG_LOW_LATENCY),
+    .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
+    .MAC_DATA_W(MAC_DATA_W)
 )
 core_inst (
     /*

src/eth/example/VCU118/fpga/rtl/fpga_core.sv

@@ -17,9 +17,16 @@ Authors:
  */
 module fpga_core #
 (
+    // simulation (set to avoid vendor primitives)
     parameter logic SIM = 1'b0,
+    // vendor ("GENERIC", "XILINX", "ALTERA")
     parameter string VENDOR = "XILINX",
-    parameter string FAMILY = "virtexuplus"
+    // device family
+    parameter string FAMILY = "virtexuplus",
+    // 10G/25G MAC configuration
+    parameter logic CFG_LOW_LATENCY = 1'b1,
+    parameter logic COMBINED_MAC_PCS = 1'b1,
+    parameter MAC_DATA_W = 64
 )
 (
     /*
@@ -481,9 +488,9 @@ wire qsfp1_mgt_refclk_0_bufg;
 
 wire qsfp_rst;
 
-taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_qsfp_tx[8]();
+taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) axis_qsfp_tx[8]();
 taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_qsfp_tx_cpl[8]();
-taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_qsfp_rx[8]();
+taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) axis_qsfp_rx[8]();
 
 if (SIM) begin
 
@@ -553,12 +560,14 @@ for (genvar n = 0; n < 2; n = n + 1) begin : gty_quad
         .CNT(4),
 
         // GT config
-        .CFG_LOW_LATENCY(1),
+        .CFG_LOW_LATENCY(CFG_LOW_LATENCY),
 
         // GT type
         .GT_TYPE("GTY"),
 
-        // PHY parameters
+        // MAC/PHY config
+        .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
+        .DATA_W(MAC_DATA_W),
         .PADDING_EN(1'b1),
         .DIC_EN(1'b1),
         .MIN_FRAME_LEN(64),

src/eth/example/VCU118/fpga/tb/fpga_core/Makefile

@@ -43,6 +43,9 @@ VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
 export PARAM_SIM := "1'b1"
 export PARAM_VENDOR := "\"XILINX\""
 export PARAM_FAMILY := "\"virtexuplus\""
+export PARAM_CFG_LOW_LATENCY := "1'b1"
+export PARAM_COMBINED_MAC_PCS := "1'b1"
+export PARAM_MAC_DATA_W := "64"
 
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst

src/eth/example/VCU118/fpga/tb/fpga_core/test_fpga_core.py

@@ -13,6 +13,7 @@ import logging
 import os
 import sys
 
+import pytest
 import cocotb_test.simulator
 
 import cocotb
@@ -61,12 +62,20 @@ class TB:
             for ch in inst.mac_inst.ch:
                 gt_inst = ch.ch_inst.gt.gt_inst
 
-                if ch.ch_inst.CFG_LOW_LATENCY.value:
-                    clk = 2.482
-                    gbx_cfg = (66, [64, 65])
+                if ch.ch_inst.DATA_W.value == 64:
+                    if ch.ch_inst.CFG_LOW_LATENCY.value:
+                        clk = 2.482
+                        gbx_cfg = (66, [64, 65])
+                    else:
+                        clk = 2.56
+                        gbx_cfg = None
                 else:
-                    clk = 2.56
-                    gbx_cfg = None
+                    if ch.ch_inst.CFG_LOW_LATENCY.value:
+                        clk = 3.102
+                        gbx_cfg = (66, [64, 65])
+                    else:
+                        clk = 3.2
+                        gbx_cfg = None
 
                 cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start())
                 cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start())
@@ -172,6 +181,8 @@ async def mac_test_25g(tb, source, sink):
     for k in range(1200):
         await RisingEdge(tb.dut.clk_125mhz)
 
+    sink.clear()
+
     tb.log.info("Multiple small packets")
 
     count = 64
@@ -254,7 +265,8 @@ def process_f_files(files):
     return list(lst.values())
 
 
-def test_fpga_core(request):
+@pytest.mark.parametrize("mac_data_w", [32, 64])
+def test_fpga_core(request, mac_data_w):
     dut = "fpga_core"
     module = os.path.splitext(os.path.basename(__file__))[0]
     toplevel = dut
@@ -279,6 +291,9 @@ def test_fpga_core(request):
     parameters['SIM'] = "1'b1"
     parameters['VENDOR'] = "\"XILINX\""
     parameters['FAMILY'] = "\"virtexuplus\""
+    parameters['CFG_LOW_LATENCY'] = "1'b1"
+    parameters['COMBINED_MAC_PCS'] = "1'b1"
+    parameters['MAC_DATA_W'] = mac_data_w
 
     extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}