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eth: More consistent handling of AN config reg value

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-07-07 00:25:48 -07:00
parent 9d11747850
commit 0d0dd238b8
2 changed files with 8 additions and 10 deletions
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9
src/eth/rtl/taxi_axis_basex_rx_8.sv
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@@ -164,7 +164,6 @@ logic m_axis_rx_tuser_reg = 1'b0, m_axis_rx_tuser_next;
logic [15:0] rx_an_cfg_reg = '0;
logic rx_an_cfg_valid_reg = 1'b0;
logic an_cfg_match_reg = 1'b0;
logic [1:0] an_ability_match_reg = '0;
logic [1:0] an_ack_match_reg = '0;
logic [1:0] an_idle_match_reg = '0;
@@ -541,21 +540,19 @@ always_ff @(posedge clk) begin
end
if (AN_EN && input_c_d0_reg) begin
rx_an_cfg_reg[7:0] <= encoded_rx_data;
an_cfg_match_reg <= rx_an_cfg_reg[7:0] == encoded_rx_data;
input_c_d1_reg <= encoded_rx_data_k == 1'b0;
an_idle_match_reg <= '0;
end
if (AN_EN && input_c_d1_reg) begin
rx_an_cfg_reg[15:8] <= encoded_rx_data;
rx_an_cfg_reg <= {encoded_rx_data, encoded_rx_data_d0_reg};
rx_an_cfg_valid_reg <= encoded_rx_data_k == 1'b0;
if (an_cfg_match_reg && ((rx_an_cfg_reg[15:8] ^ encoded_rx_data) & ~8'h40) == 0) begin
if (((rx_an_cfg_reg ^ {encoded_rx_data, encoded_rx_data_d0_reg}) & ~16'h4000) == 0) begin
an_ability_match_reg <= {an_ability_match_reg[0], 1'b1};
end else begin
an_ability_match_reg <= '0;
end
if (an_cfg_match_reg && rx_an_cfg_reg[14] && rx_an_cfg_reg[15:8] == encoded_rx_data) begin
if (rx_an_cfg_reg[14] && rx_an_cfg_reg == {encoded_rx_data, encoded_rx_data_d0_reg}) begin
an_ack_match_reg <= {an_ack_match_reg[0], 1'b1};
end else begin
an_ack_match_reg <= '0;

9
src/eth/rtl/taxi_axis_basex_tx_8.sv
View File

@@ -669,12 +669,13 @@ always_comb begin
// send config register
if (!odd_reg) begin
encoded_tx_data_next = tx_an_cfg[7:0];
encoded_tx_data_k_next = 1'b0;
state_next = STATE_AN;
end else begin
encoded_tx_data_next = tx_an_cfg[15:8];
s_tdata_next = tx_an_cfg[15:8];
encoded_tx_data_k_next = 1'b0;
tx_an_cfg_ready_next = 1'b1;
state_next = STATE_AN;
end else begin
encoded_tx_data_next = s_tdata_reg;
encoded_tx_data_k_next = 1'b0;
an_phase_next = !an_phase_reg;
state_next = STATE_IDLE;
end