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eth: Fix 2D array declarations

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-10-04 11:02:30 -07:00
parent 5dff55ec06
commit 0e2acbf482
4 changed files with 8 additions and 8 deletions
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4
src/eth/rtl/taxi_axis_baser_tx_32.sv
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@@ -204,8 +204,8 @@ logic [PTP_TS_W-1:0] m_axis_tx_cpl_ts_reg = '0, m_axis_tx_cpl_ts_next;
logic [TX_TAG_W-1:0] m_axis_tx_cpl_tag_reg = '0, m_axis_tx_cpl_tag_next;
logic m_axis_tx_cpl_valid_reg = 1'b0, m_axis_tx_cpl_valid_next;
logic [31:0] crc_state_reg[3:0];
wire [31:0] crc_state_next[3:0];
logic [31:0] crc_state_reg[4];
wire [31:0] crc_state_next[4];
logic [DATA_W-1:0] encoded_tx_data_reg = {24'd0, BLOCK_TYPE_CTRL};
logic encoded_tx_data_valid_reg = 1'b0;

4
src/eth/rtl/taxi_axis_baser_tx_64.sv
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@@ -218,8 +218,8 @@ logic m_axis_tx_cpl_valid_reg = 1'b0;
logic m_axis_tx_cpl_valid_int_reg = 1'b0;
logic m_axis_tx_cpl_ts_borrow_reg = 1'b0;
logic [31:0] crc_state_reg[7:0];
wire [31:0] crc_state_next[7:0];
logic [31:0] crc_state_reg[8];
wire [31:0] crc_state_next[8];
logic [DATA_W-1:0] encoded_tx_data_reg = {{8{CTRL_IDLE}}, BLOCK_TYPE_CTRL};
logic encoded_tx_data_valid_reg = 1'b0;

4
src/eth/rtl/taxi_axis_xgmii_tx_32.sv
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@@ -160,8 +160,8 @@ logic [PTP_TS_W-1:0] m_axis_tx_cpl_ts_reg = '0, m_axis_tx_cpl_ts_next;
logic [TX_TAG_W-1:0] m_axis_tx_cpl_tag_reg = '0, m_axis_tx_cpl_tag_next;
logic m_axis_tx_cpl_valid_reg = 1'b0, m_axis_tx_cpl_valid_next;
logic [31:0] crc_state_reg[3:0];
wire [31:0] crc_state_next[3:0];
logic [31:0] crc_state_reg[4];
wire [31:0] crc_state_next[4];
logic [DATA_W-1:0] xgmii_txd_reg = {CTRL_W{XGMII_IDLE}}, xgmii_txd_next;
logic [CTRL_W-1:0] xgmii_txc_reg = {CTRL_W{1'b1}}, xgmii_txc_next;

4
src/eth/rtl/taxi_axis_xgmii_tx_64.sv
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@@ -165,8 +165,8 @@ logic m_axis_tx_cpl_valid_reg = 1'b0;
logic m_axis_tx_cpl_valid_int_reg = 1'b0;
logic m_axis_tx_cpl_ts_borrow_reg = 1'b0;
logic [31:0] crc_state_reg[7:0];
wire [31:0] crc_state_next[7:0];
logic [31:0] crc_state_reg[8];
wire [31:0] crc_state_next[8];
logic [4+16-1:0] last_ts_reg = '0;
logic [4+16-1:0] ts_inc_reg = '0;