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eth: Update example designs

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-10-02 16:11:07 -07:00
parent 76d4465081
commit 159c9d6241
45 changed files with 1561 additions and 1296 deletions
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69
src/eth/example/Alveo/fpga/rtl/fpga_au200.sv
View File

@@ -48,10 +48,10 @@ module fpga #
/*
* Ethernet: QSFP28
*/
output wire logic [3:0] qsfp0_tx_p,
output wire logic [3:0] qsfp0_tx_n,
input wire logic [3:0] qsfp0_rx_p,
input wire logic [3:0] qsfp0_rx_n,
output wire logic qsfp0_tx_p[4],
output wire logic qsfp0_tx_n[4],
input wire logic qsfp0_rx_p[4],
input wire logic qsfp0_rx_n[4],
input wire logic qsfp0_mgt_refclk_0_p,
input wire logic qsfp0_mgt_refclk_0_n,
// input wire logic qsfp0_mgt_refclk_1_p,
@@ -64,10 +64,10 @@ module fpga #
// output wire logic qsfp0_refclk_reset,
// output wire logic [1:0] qsfp0_fs,
output wire logic [3:0] qsfp1_tx_p,
output wire logic [3:0] qsfp1_tx_n,
input wire logic [3:0] qsfp1_rx_p,
input wire logic [3:0] qsfp1_rx_n,
output wire logic qsfp1_tx_p[4],
output wire logic qsfp1_tx_n[4],
input wire logic qsfp1_rx_p[4],
input wire logic qsfp1_rx_n[4],
input wire logic qsfp1_mgt_refclk_0_p,
input wire logic qsfp1_mgt_refclk_0_n,
// input wire logic qsfp1_mgt_refclk_1_p,
@@ -215,10 +215,35 @@ assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
assign i2c_sda_i = i2c_sda;
assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
wire qsfp0_mgt_refclk_0;
wire qsfp1_mgt_refclk_0;
localparam PORT_CNT = 2;
localparam GTY_QUAD_CNT = PORT_CNT;
localparam GTY_CNT = GTY_QUAD_CNT*4;
localparam GTY_CLK_CNT = GTY_QUAD_CNT;
assign clk_156mhz_ref_int = qsfp0_mgt_refclk_0;
wire eth_gty_tx_p[GTY_CNT];
wire eth_gty_tx_n[GTY_CNT];
wire eth_gty_rx_p[GTY_CNT];
wire eth_gty_rx_n[GTY_CNT];
wire eth_gty_mgt_refclk_p[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_n[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_out[GTY_CLK_CNT];
assign qsfp0_tx_p = eth_gty_tx_p[4*0 +: 4];
assign qsfp0_tx_n = eth_gty_tx_n[4*0 +: 4];
assign eth_gty_rx_p[4*0 +: 4] = qsfp0_rx_p;
assign eth_gty_rx_n[4*0 +: 4] = qsfp0_rx_n;
assign qsfp1_tx_p = eth_gty_tx_p[4*1 +: 4];
assign qsfp1_tx_n = eth_gty_tx_n[4*1 +: 4];
assign eth_gty_rx_p[4*1 +: 4] = qsfp1_rx_p;
assign eth_gty_rx_n[4*1 +: 4] = qsfp1_rx_n;
assign eth_gty_mgt_refclk_p[0] = qsfp0_mgt_refclk_0_p;
assign eth_gty_mgt_refclk_n[0] = qsfp0_mgt_refclk_0_n;
assign eth_gty_mgt_refclk_p[1] = qsfp1_mgt_refclk_0_p;
assign eth_gty_mgt_refclk_n[1] = qsfp1_mgt_refclk_0_n;
assign clk_156mhz_ref_int = eth_gty_mgt_refclk_out[0];
fpga_core #(
.SIM(SIM),
@@ -227,10 +252,10 @@ fpga_core #(
.SW_CNT(4),
.LED_CNT(3),
.UART_CNT(1),
.PORT_CNT(2),
.GTY_QUAD_CNT(2),
.GTY_CNT(2*4),
.GTY_CLK_CNT(2)
.PORT_CNT(PORT_CNT),
.GTY_QUAD_CNT(GTY_QUAD_CNT),
.GTY_CNT(GTY_CNT),
.GTY_CLK_CNT(GTY_CLK_CNT)
)
core_inst (
/*
@@ -260,13 +285,13 @@ core_inst (
/*
* Ethernet
*/
.eth_gty_tx_p({qsfp1_tx_p, qsfp0_tx_p}),
.eth_gty_tx_n({qsfp1_tx_n, qsfp0_tx_n}),
.eth_gty_rx_p({qsfp1_rx_p, qsfp0_rx_p}),
.eth_gty_rx_n({qsfp1_rx_n, qsfp0_rx_n}),
.eth_gty_mgt_refclk_p({qsfp1_mgt_refclk_0_p, qsfp0_mgt_refclk_0_p}),
.eth_gty_mgt_refclk_n({qsfp1_mgt_refclk_0_n, qsfp0_mgt_refclk_0_n}),
.eth_gty_mgt_refclk_out({qsfp1_mgt_refclk_0, qsfp0_mgt_refclk_0}),
.eth_gty_tx_p(eth_gty_tx_p),
.eth_gty_tx_n(eth_gty_tx_n),
.eth_gty_rx_p(eth_gty_rx_p),
.eth_gty_rx_n(eth_gty_rx_n),
.eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p),
.eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n),
.eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out),
.eth_port_modsell({qsfp1_modsell, qsfp0_modsell}),
.eth_port_resetl({qsfp1_resetl, qsfp0_resetl}),

69
src/eth/example/Alveo/fpga/rtl/fpga_au280.sv
View File

@@ -41,10 +41,10 @@ module fpga #
/*
* Ethernet: QSFP28
*/
output wire logic [3:0] qsfp0_tx_p,
output wire logic [3:0] qsfp0_tx_n,
input wire logic [3:0] qsfp0_rx_p,
input wire logic [3:0] qsfp0_rx_n,
output wire logic qsfp0_tx_p[4],
output wire logic qsfp0_tx_n[4],
input wire logic qsfp0_rx_p[4],
input wire logic qsfp0_rx_n[4],
input wire logic qsfp0_mgt_refclk_0_p,
input wire logic qsfp0_mgt_refclk_0_n,
// input wire logic qsfp0_mgt_refclk_1_p,
@@ -52,10 +52,10 @@ module fpga #
output wire logic qsfp0_refclk_oe_b,
output wire logic qsfp0_refclk_fs,
output wire logic [3:0] qsfp1_tx_p,
output wire logic [3:0] qsfp1_tx_n,
input wire logic [3:0] qsfp1_rx_p,
input wire logic [3:0] qsfp1_rx_n,
output wire logic qsfp1_tx_p[4],
output wire logic qsfp1_tx_n[4],
input wire logic qsfp1_rx_p[4],
input wire logic qsfp1_rx_n[4],
input wire logic qsfp1_mgt_refclk_0_p,
input wire logic qsfp1_mgt_refclk_0_n,
// input wire logic qsfp1_mgt_refclk_1_p,
@@ -178,10 +178,35 @@ assign qsfp0_refclk_fs = 1'b1;
assign qsfp1_refclk_oe_b = 1'b0;
assign qsfp1_refclk_fs = 1'b1;
wire qsfp0_mgt_refclk_0;
wire qsfp1_mgt_refclk_0;
localparam PORT_CNT = 2;
localparam GTY_QUAD_CNT = PORT_CNT;
localparam GTY_CNT = GTY_QUAD_CNT*4;
localparam GTY_CLK_CNT = GTY_QUAD_CNT;
assign clk_156mhz_ref_int = qsfp0_mgt_refclk_0;
wire eth_gty_tx_p[GTY_CNT];
wire eth_gty_tx_n[GTY_CNT];
wire eth_gty_rx_p[GTY_CNT];
wire eth_gty_rx_n[GTY_CNT];
wire eth_gty_mgt_refclk_p[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_n[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_out[GTY_CLK_CNT];
assign qsfp0_tx_p = eth_gty_tx_p[4*0 +: 4];
assign qsfp0_tx_n = eth_gty_tx_n[4*0 +: 4];
assign eth_gty_rx_p[4*0 +: 4] = qsfp0_rx_p;
assign eth_gty_rx_n[4*0 +: 4] = qsfp0_rx_n;
assign qsfp1_tx_p = eth_gty_tx_p[4*1 +: 4];
assign qsfp1_tx_n = eth_gty_tx_n[4*1 +: 4];
assign eth_gty_rx_p[4*1 +: 4] = qsfp1_rx_p;
assign eth_gty_rx_n[4*1 +: 4] = qsfp1_rx_n;
assign eth_gty_mgt_refclk_p[0] = qsfp0_mgt_refclk_0_p;
assign eth_gty_mgt_refclk_n[0] = qsfp0_mgt_refclk_0_n;
assign eth_gty_mgt_refclk_p[1] = qsfp1_mgt_refclk_0_p;
assign eth_gty_mgt_refclk_n[1] = qsfp1_mgt_refclk_0_n;
assign clk_156mhz_ref_int = eth_gty_mgt_refclk_out[0];
fpga_core #(
.SIM(SIM),
@@ -190,10 +215,10 @@ fpga_core #(
.SW_CNT(4),
.LED_CNT(3),
.UART_CNT(1),
.PORT_CNT(2),
.GTY_QUAD_CNT(2),
.GTY_CNT(2*4),
.GTY_CLK_CNT(2)
.PORT_CNT(PORT_CNT),
.GTY_QUAD_CNT(GTY_QUAD_CNT),
.GTY_CNT(GTY_CNT),
.GTY_CLK_CNT(GTY_CLK_CNT)
)
core_inst (
/*
@@ -223,13 +248,13 @@ core_inst (
/*
* Ethernet
*/
.eth_gty_tx_p({qsfp1_tx_p, qsfp0_tx_p}),
.eth_gty_tx_n({qsfp1_tx_n, qsfp0_tx_n}),
.eth_gty_rx_p({qsfp1_rx_p, qsfp0_rx_p}),
.eth_gty_rx_n({qsfp1_rx_n, qsfp0_rx_n}),
.eth_gty_mgt_refclk_p({qsfp1_mgt_refclk_0_p, qsfp0_mgt_refclk_0_p}),
.eth_gty_mgt_refclk_n({qsfp1_mgt_refclk_0_n, qsfp0_mgt_refclk_0_n}),
.eth_gty_mgt_refclk_out({qsfp1_mgt_refclk_0, qsfp0_mgt_refclk_0}),
.eth_gty_tx_p(eth_gty_tx_p),
.eth_gty_tx_n(eth_gty_tx_n),
.eth_gty_rx_p(eth_gty_rx_p),
.eth_gty_rx_n(eth_gty_rx_n),
.eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p),
.eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n),
.eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out),
.eth_port_modsell(),
.eth_port_resetl(),

61
src/eth/example/Alveo/fpga/rtl/fpga_au45n.sv
View File

@@ -42,19 +42,19 @@ module fpga #
/*
* Ethernet: QSFP28
*/
// output wire logic [3:0] qsfp0_tx_p,
// output wire logic [3:0] qsfp0_tx_n,
// input wire logic [3:0] qsfp0_rx_p,
// input wire logic [3:0] qsfp0_rx_n,
// output wire logic qsfp0_tx_p[4],
// output wire logic qsfp0_tx_n[4],
// input wire logic qsfp0_rx_p[4],
// input wire logic qsfp0_rx_n[4],
// input wire logic qsfp0_mgt_refclk_0_p,
// input wire logic qsfp0_mgt_refclk_0_n,
// input wire logic qsfp0_mgt_refclk_1_p,
// input wire logic qsfp0_mgt_refclk_1_n,
output wire logic [3:0] qsfp1_tx_p,
output wire logic [3:0] qsfp1_tx_n,
input wire logic [3:0] qsfp1_rx_p,
input wire logic [3:0] qsfp1_rx_n,
output wire logic qsfp1_tx_p[4],
output wire logic qsfp1_tx_n[4],
input wire logic qsfp1_rx_p[4],
input wire logic qsfp1_rx_n[4],
input wire logic qsfp1_mgt_refclk_p,
input wire logic qsfp1_mgt_refclk_n
);
@@ -165,9 +165,28 @@ sync_reset_125mhz_inst (
.out(rst_125mhz_int)
);
wire qsfp1_mgt_refclk;
localparam PORT_CNT = QSFP_CNT;
localparam GTY_QUAD_CNT = 1;
localparam GTY_CNT = GTY_QUAD_CNT*4;
localparam GTY_CLK_CNT = GTY_QUAD_CNT;
assign clk_161mhz_ref_int = qsfp1_mgt_refclk;
wire eth_gty_tx_p[GTY_CNT];
wire eth_gty_tx_n[GTY_CNT];
wire eth_gty_rx_p[GTY_CNT];
wire eth_gty_rx_n[GTY_CNT];
wire eth_gty_mgt_refclk_p[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_n[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_out[GTY_CLK_CNT];
assign qsfp1_tx_p = eth_gty_tx_p[4*0 +: 4];
assign qsfp1_tx_n = eth_gty_tx_n[4*0 +: 4];
assign eth_gty_rx_p[4*0 +: 4] = qsfp1_rx_p;
assign eth_gty_rx_n[4*0 +: 4] = qsfp1_rx_n;
assign eth_gty_mgt_refclk_p[0] = qsfp1_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[0] = qsfp1_mgt_refclk_n;
assign clk_161mhz_ref_int = eth_gty_mgt_refclk_out[0];
fpga_core #(
.SIM(SIM),
@@ -176,10 +195,10 @@ fpga_core #(
.SW_CNT(4),
.LED_CNT(2),
.UART_CNT(UART_CNT),
.PORT_CNT(QSFP_CNT),
.GTY_QUAD_CNT(1),
.GTY_CNT(1*4),
.GTY_CLK_CNT(1)
.PORT_CNT(PORT_CNT),
.GTY_QUAD_CNT(GTY_QUAD_CNT),
.GTY_CNT(GTY_CNT),
.GTY_CLK_CNT(GTY_CLK_CNT)
)
core_inst (
/*
@@ -209,13 +228,13 @@ core_inst (
/*
* Ethernet
*/
.eth_gty_tx_p(qsfp1_tx_p),
.eth_gty_tx_n(qsfp1_tx_n),
.eth_gty_rx_p(qsfp1_rx_p),
.eth_gty_rx_n(qsfp1_rx_n),
.eth_gty_mgt_refclk_p(qsfp1_mgt_refclk_p),
.eth_gty_mgt_refclk_n(qsfp1_mgt_refclk_n),
.eth_gty_mgt_refclk_out(qsfp1_mgt_refclk),
.eth_gty_tx_p(eth_gty_tx_p),
.eth_gty_tx_n(eth_gty_tx_n),
.eth_gty_rx_p(eth_gty_rx_p),
.eth_gty_rx_n(eth_gty_rx_n),
.eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p),
.eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n),
.eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out),
.eth_port_modsell(),
.eth_port_resetl(),

53
src/eth/example/Alveo/fpga/rtl/fpga_au50.sv
View File

@@ -41,10 +41,10 @@ module fpga #
/*
* Ethernet: QSFP28
*/
output wire logic [3:0] qsfp_tx_p,
output wire logic [3:0] qsfp_tx_n,
input wire logic [3:0] qsfp_rx_p,
input wire logic [3:0] qsfp_rx_n,
output wire logic qsfp_tx_p[4],
output wire logic qsfp_tx_n[4],
input wire logic qsfp_rx_p[4],
input wire logic qsfp_rx_n[4],
input wire logic qsfp_mgt_refclk_0_p,
input wire logic qsfp_mgt_refclk_0_n
// input wire logic qsfp_mgt_refclk_1_p,
@@ -160,9 +160,28 @@ sync_reset_125mhz_inst (
// GPIO
assign hbm_cattrip = 1'b0;
wire qsfp_mgt_refclk_0;
localparam PORT_CNT = QSFP_CNT;
localparam GTY_QUAD_CNT = PORT_CNT;
localparam GTY_CNT = GTY_QUAD_CNT*4;
localparam GTY_CLK_CNT = GTY_QUAD_CNT;
assign clk_161mhz_ref_int = qsfp_mgt_refclk_0;
wire eth_gty_tx_p[GTY_CNT];
wire eth_gty_tx_n[GTY_CNT];
wire eth_gty_rx_p[GTY_CNT];
wire eth_gty_rx_n[GTY_CNT];
wire eth_gty_mgt_refclk_p[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_n[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_out[GTY_CLK_CNT];
assign qsfp_tx_p = eth_gty_tx_p[4*0 +: 4];
assign qsfp_tx_n = eth_gty_tx_n[4*0 +: 4];
assign eth_gty_rx_p[4*0 +: 4] = qsfp_rx_p;
assign eth_gty_rx_n[4*0 +: 4] = qsfp_rx_n;
assign eth_gty_mgt_refclk_p[0] = qsfp_mgt_refclk_0_p;
assign eth_gty_mgt_refclk_n[0] = qsfp_mgt_refclk_0_n;
assign clk_161mhz_ref_int = eth_gty_mgt_refclk_out[0];
fpga_core #(
.SIM(SIM),
@@ -171,10 +190,10 @@ fpga_core #(
.SW_CNT(4),
.LED_CNT(3),
.UART_CNT(UART_CNT),
.PORT_CNT(QSFP_CNT),
.GTY_QUAD_CNT(QSFP_CNT),
.GTY_CNT(QSFP_CNT*4),
.GTY_CLK_CNT(QSFP_CNT)
.PORT_CNT(PORT_CNT),
.GTY_QUAD_CNT(GTY_QUAD_CNT),
.GTY_CNT(GTY_CNT),
.GTY_CLK_CNT(GTY_CLK_CNT)
)
core_inst (
/*
@@ -204,13 +223,13 @@ core_inst (
/*
* Ethernet
*/
.eth_gty_tx_p(qsfp_tx_p),
.eth_gty_tx_n(qsfp_tx_n),
.eth_gty_rx_p(qsfp_rx_p),
.eth_gty_rx_n(qsfp_rx_n),
.eth_gty_mgt_refclk_p(qsfp_mgt_refclk_0_p),
.eth_gty_mgt_refclk_n(qsfp_mgt_refclk_0_n),
.eth_gty_mgt_refclk_out(qsfp_mgt_refclk_0),
.eth_gty_tx_p(eth_gty_tx_p),
.eth_gty_tx_n(eth_gty_tx_n),
.eth_gty_rx_p(eth_gty_rx_p),
.eth_gty_rx_n(eth_gty_rx_n),
.eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p),
.eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n),
.eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out),
.eth_port_modsell(),
.eth_port_resetl(),

69
src/eth/example/Alveo/fpga/rtl/fpga_au55.sv
View File

@@ -46,17 +46,17 @@ module fpga #
/*
* Ethernet: QSFP28
*/
output wire logic [3:0] qsfp0_tx_p,
output wire logic [3:0] qsfp0_tx_n,
input wire logic [3:0] qsfp0_rx_p,
input wire logic [3:0] qsfp0_rx_n,
output wire logic qsfp0_tx_p[4],
output wire logic qsfp0_tx_n[4],
input wire logic qsfp0_rx_p[4],
input wire logic qsfp0_rx_n[4],
input wire logic qsfp0_mgt_refclk_p,
input wire logic qsfp0_mgt_refclk_n,
output wire logic [3:0] qsfp1_tx_p,
output wire logic [3:0] qsfp1_tx_n,
input wire logic [3:0] qsfp1_rx_p,
input wire logic [3:0] qsfp1_rx_n,
output wire logic qsfp1_tx_p[4],
output wire logic qsfp1_tx_n[4],
input wire logic qsfp1_rx_p[4],
input wire logic qsfp1_rx_n[4],
input wire logic qsfp1_mgt_refclk_p,
input wire logic qsfp1_mgt_refclk_n
);
@@ -170,10 +170,35 @@ sync_reset_125mhz_inst (
// GPIO
assign hbm_cattrip = 1'b0;
wire qsfp0_mgt_refclk;
wire qsfp1_mgt_refclk;
localparam PORT_CNT = QSFP_CNT;
localparam GTY_QUAD_CNT = PORT_CNT;
localparam GTY_CNT = GTY_QUAD_CNT*4;
localparam GTY_CLK_CNT = GTY_QUAD_CNT;
assign clk_161mhz_ref_int = qsfp0_mgt_refclk;
wire eth_gty_tx_p[GTY_CNT];
wire eth_gty_tx_n[GTY_CNT];
wire eth_gty_rx_p[GTY_CNT];
wire eth_gty_rx_n[GTY_CNT];
wire eth_gty_mgt_refclk_p[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_n[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_out[GTY_CLK_CNT];
assign qsfp0_tx_p = eth_gty_tx_p[4*0 +: 4];
assign qsfp0_tx_n = eth_gty_tx_n[4*0 +: 4];
assign eth_gty_rx_p[4*0 +: 4] = qsfp0_rx_p;
assign eth_gty_rx_n[4*0 +: 4] = qsfp0_rx_n;
assign qsfp1_tx_p = eth_gty_tx_p[4*1 +: 4];
assign qsfp1_tx_n = eth_gty_tx_n[4*1 +: 4];
assign eth_gty_rx_p[4*1 +: 4] = qsfp1_rx_p;
assign eth_gty_rx_n[4*1 +: 4] = qsfp1_rx_n;
assign eth_gty_mgt_refclk_p[0] = qsfp0_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[0] = qsfp0_mgt_refclk_n;
assign eth_gty_mgt_refclk_p[1] = qsfp1_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[1] = qsfp1_mgt_refclk_n;
assign clk_161mhz_ref_int = eth_gty_mgt_refclk_out[0];
fpga_core #(
.SIM(SIM),
@@ -182,10 +207,10 @@ fpga_core #(
.SW_CNT(4),
.LED_CNT(3),
.UART_CNT(UART_CNT),
.PORT_CNT(QSFP_CNT),
.GTY_QUAD_CNT(QSFP_CNT),
.GTY_CNT(QSFP_CNT*4),
.GTY_CLK_CNT(QSFP_CNT)
.PORT_CNT(PORT_CNT),
.GTY_QUAD_CNT(GTY_QUAD_CNT),
.GTY_CNT(GTY_CNT),
.GTY_CLK_CNT(GTY_CLK_CNT)
)
core_inst (
/*
@@ -215,13 +240,13 @@ core_inst (
/*
* Ethernet
*/
.eth_gty_tx_p({qsfp1_tx_p, qsfp0_tx_p}),
.eth_gty_tx_n({qsfp1_tx_n, qsfp0_tx_n}),
.eth_gty_rx_p({qsfp1_rx_p, qsfp0_rx_p}),
.eth_gty_rx_n({qsfp1_rx_n, qsfp0_rx_n}),
.eth_gty_mgt_refclk_p({qsfp1_mgt_refclk_p, qsfp0_mgt_refclk_p}),
.eth_gty_mgt_refclk_n({qsfp1_mgt_refclk_n, qsfp0_mgt_refclk_n}),
.eth_gty_mgt_refclk_out({qsfp1_mgt_refclk, qsfp0_mgt_refclk}),
.eth_gty_tx_p(eth_gty_tx_p),
.eth_gty_tx_n(eth_gty_tx_n),
.eth_gty_rx_p(eth_gty_rx_p),
.eth_gty_rx_n(eth_gty_rx_n),
.eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p),
.eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n),
.eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out),
.eth_port_modsell(),
.eth_port_resetl(),

86
src/eth/example/Alveo/fpga/rtl/fpga_core.sv
View File

@@ -57,13 +57,13 @@ module fpga_core #
/*
* Ethernet
*/
output wire logic [GTY_CNT-1:0] eth_gty_tx_p,
output wire logic [GTY_CNT-1:0] eth_gty_tx_n,
input wire logic [GTY_CNT-1:0] eth_gty_rx_p,
input wire logic [GTY_CNT-1:0] eth_gty_rx_n,
input wire logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_p,
input wire logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_n,
output wire logic [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_out,
output wire logic eth_gty_tx_p[GTY_CNT],
output wire logic eth_gty_tx_n[GTY_CNT],
input wire logic eth_gty_rx_p[GTY_CNT],
input wire logic eth_gty_rx_n[GTY_CNT],
input wire logic eth_gty_mgt_refclk_p[GTY_CLK_CNT],
input wire logic eth_gty_mgt_refclk_n[GTY_CLK_CNT],
output wire logic eth_gty_mgt_refclk_out[GTY_CLK_CNT],
output wire logic [PORT_CNT-1:0] eth_port_modsell,
output wire logic [PORT_CNT-1:0] eth_port_resetl,
@@ -221,23 +221,23 @@ assign eth_port_modsell = '1;
assign eth_port_resetl = '1;
assign eth_port_lpmode = '0;
wire [GTY_CNT-1:0] eth_gty_tx_clk;
wire [GTY_CNT-1:0] eth_gty_tx_rst;
wire eth_gty_tx_clk[GTY_CNT];
wire eth_gty_tx_rst[GTY_CNT];
taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_tx[GTY_CNT]();
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) eth_gty_axis_tx_cpl[GTY_CNT]();
wire [GTY_CNT-1:0] eth_gty_rx_clk;
wire [GTY_CNT-1:0] eth_gty_rx_rst;
wire eth_gty_rx_clk[GTY_CNT];
wire eth_gty_rx_rst[GTY_CNT];
taxi_axis_if #(.DATA_W(64), .ID_W(8)) eth_gty_axis_rx[GTY_CNT]();
wire [GTY_CNT-1:0] eth_gty_rx_status;
wire eth_gty_rx_status[GTY_CNT];
wire [GTY_QUAD_CNT-1:0] eth_gty_gtpowergood;
wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk;
wire [GTY_CLK_CNT-1:0] eth_gty_mgt_refclk_bufg;
wire eth_gty_mgt_refclk[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_bufg[GTY_CLK_CNT];
wire [GTY_CLK_CNT-1:0] eth_gty_rst;
wire eth_gty_rst[GTY_CLK_CNT];
for (genvar n = 0; n < GTY_CLK_CNT; n = n + 1) begin : gty_clk
@@ -359,12 +359,12 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
* MAC clocks
*/
.rx_clk(eth_gty_rx_clk[n*CNT +: CNT]),
.rx_rst_in('0),
.rx_rst_in('{CNT{1'b0}}),
.rx_rst_out(eth_gty_rx_rst[n*CNT +: CNT]),
.tx_clk(eth_gty_tx_clk[n*CNT +: CNT]),
.tx_rst_in('0),
.tx_rst_in('{CNT{1'b0}}),
.tx_rst_out(eth_gty_tx_rst[n*CNT +: CNT]),
.ptp_sample_clk('0),
.ptp_sample_clk('{CNT{1'b0}}),
/*
* Transmit interface (AXI stream)
@@ -381,24 +381,24 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
* PTP clock
*/
.tx_ptp_ts('{CNT{'0}}),
.tx_ptp_ts_step('0),
.tx_ptp_ts_step('{CNT{1'b0}}),
.rx_ptp_ts('{CNT{'0}}),
.rx_ptp_ts_step('0),
.rx_ptp_ts_step('{CNT{1'b0}}),
/*
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
*/
.tx_lfc_req('0),
.tx_lfc_resend('0),
.rx_lfc_en('0),
.tx_lfc_req('{CNT{1'b0}}),
.tx_lfc_resend('{CNT{1'b0}}),
.rx_lfc_en('{CNT{1'b0}}),
.rx_lfc_req(),
.rx_lfc_ack('0),
.rx_lfc_ack('{CNT{1'b0}}),
/*
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
*/
.tx_pfc_req('{CNT{'0}}),
.tx_pfc_resend('0),
.tx_pfc_resend('{CNT{1'b0}}),
.rx_pfc_en('{CNT{'0}}),
.rx_pfc_req(),
.rx_pfc_ack('{CNT{'0}}),
@@ -406,8 +406,8 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
/*
* Pause interface
*/
.tx_lfc_pause_en('0),
.tx_pause_req('0),
.tx_lfc_pause_en('{CNT{1'b0}}),
.tx_pause_req('{CNT{1'b0}}),
.tx_pause_ack(),
/*
@@ -452,7 +452,7 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
.stat_rx_err_bad_block(),
.stat_rx_err_framing(),
.stat_rx_err_preamble(),
.stat_rx_fifo_drop('0),
.stat_rx_fifo_drop('{CNT{1'b0}}),
.stat_tx_mcf(),
.stat_rx_mcf(),
.stat_tx_lfc_pkt(),
@@ -477,42 +477,42 @@ for (genvar n = 0; n < GTY_QUAD_CNT; n = n + 1) begin : gty_quad
*/
.cfg_tx_max_pkt_len('{CNT{16'd9218}}),
.cfg_tx_ifg('{CNT{8'd12}}),
.cfg_tx_enable('1),
.cfg_tx_enable('{CNT{1'b1}}),
.cfg_rx_max_pkt_len('{CNT{16'd9218}}),
.cfg_rx_enable('1),
.cfg_tx_prbs31_enable('0),
.cfg_rx_prbs31_enable('0),
.cfg_rx_enable('{CNT{1'b1}}),
.cfg_tx_prbs31_enable('{CNT{1'b0}}),
.cfg_rx_prbs31_enable('{CNT{1'b0}}),
.cfg_mcf_rx_eth_dst_mcast('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_mcf_rx_check_eth_dst_mcast('1),
.cfg_mcf_rx_check_eth_dst_mcast('{CNT{1'b1}}),
.cfg_mcf_rx_eth_dst_ucast('{CNT{48'd0}}),
.cfg_mcf_rx_check_eth_dst_ucast('0),
.cfg_mcf_rx_check_eth_dst_ucast('{CNT{1'b0}}),
.cfg_mcf_rx_eth_src('{CNT{48'd0}}),
.cfg_mcf_rx_check_eth_src('0),
.cfg_mcf_rx_check_eth_src('{CNT{1'b0}}),
.cfg_mcf_rx_eth_type('{CNT{16'h8808}}),
.cfg_mcf_rx_opcode_lfc('{CNT{16'h0001}}),
.cfg_mcf_rx_check_opcode_lfc('1),
.cfg_mcf_rx_check_opcode_lfc('{CNT{1'b1}}),
.cfg_mcf_rx_opcode_pfc('{CNT{16'h0101}}),
.cfg_mcf_rx_check_opcode_pfc('1),
.cfg_mcf_rx_forward('0),
.cfg_mcf_rx_enable('0),
.cfg_mcf_rx_check_opcode_pfc('{CNT{1'b1}}),
.cfg_mcf_rx_forward('{CNT{1'b0}}),
.cfg_mcf_rx_enable('{CNT{1'b0}}),
.cfg_tx_lfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_tx_lfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
.cfg_tx_lfc_eth_type('{CNT{16'h8808}}),
.cfg_tx_lfc_opcode('{CNT{16'h0001}}),
.cfg_tx_lfc_en('0),
.cfg_tx_lfc_en('{CNT{1'b0}}),
.cfg_tx_lfc_quanta('{CNT{16'hffff}}),
.cfg_tx_lfc_refresh('{CNT{16'h7fff}}),
.cfg_tx_pfc_eth_dst('{CNT{48'h01_80_C2_00_00_01}}),
.cfg_tx_pfc_eth_src('{CNT{48'h80_23_31_43_54_4C}}),
.cfg_tx_pfc_eth_type('{CNT{16'h8808}}),
.cfg_tx_pfc_opcode('{CNT{16'h0101}}),
.cfg_tx_pfc_en('0),
.cfg_tx_pfc_en('{CNT{1'b0}}),
.cfg_tx_pfc_quanta('{CNT{'{8{16'hffff}}}}),
.cfg_tx_pfc_refresh('{CNT{'{8{16'h7fff}}}}),
.cfg_rx_lfc_opcode('{CNT{16'h0001}}),
.cfg_rx_lfc_en('0),
.cfg_rx_lfc_en('{CNT{1'b0}}),
.cfg_rx_pfc_opcode('{CNT{16'h0101}}),
.cfg_rx_pfc_en('0)
.cfg_rx_pfc_en('{CNT{1'b0}})
);
end

63
src/eth/example/Alveo/fpga/rtl/fpga_x3522.sv
View File

@@ -40,14 +40,14 @@ module fpga #
/*
* Ethernet: QSFP28
*/
output wire logic [1:0] dsfp0_tx_p,
output wire logic [1:0] dsfp0_tx_n,
input wire logic [1:0] dsfp0_rx_p,
input wire logic [1:0] dsfp0_rx_n,
output wire logic [1:0] dsfp1_tx_p,
output wire logic [1:0] dsfp1_tx_n,
input wire logic [1:0] dsfp1_rx_p,
input wire logic [1:0] dsfp1_rx_n,
output wire logic dsfp0_tx_p[2],
output wire logic dsfp0_tx_n[2],
input wire logic dsfp0_rx_p[2],
input wire logic dsfp0_rx_n[2],
output wire logic dsfp1_tx_p[2],
output wire logic dsfp1_tx_n[2],
input wire logic dsfp1_rx_p[2],
input wire logic dsfp1_rx_n[2],
input wire logic dsfp_mgt_refclk_p,
input wire logic dsfp_mgt_refclk_n
);
@@ -158,9 +158,32 @@ sync_reset_125mhz_inst (
.out(rst_125mhz_int)
);
wire dsfp_mgt_refclk;
localparam GTY_QUAD_CNT = 1;
localparam GTY_CNT = GTY_QUAD_CNT*4;
localparam GTY_CLK_CNT = GTY_QUAD_CNT;
assign clk_161mhz_ref_int = dsfp_mgt_refclk;
wire eth_gty_tx_p[GTY_CNT];
wire eth_gty_tx_n[GTY_CNT];
wire eth_gty_rx_p[GTY_CNT];
wire eth_gty_rx_n[GTY_CNT];
wire eth_gty_mgt_refclk_p[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_n[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_out[GTY_CLK_CNT];
assign dsfp0_tx_p = eth_gty_tx_p[2*0 +: 2];
assign dsfp0_tx_n = eth_gty_tx_n[2*0 +: 2];
assign eth_gty_rx_p[2*0 +: 2] = dsfp0_rx_p;
assign eth_gty_rx_n[2*0 +: 2] = dsfp0_rx_n;
assign dsfp1_tx_p = eth_gty_tx_p[2*1 +: 2];
assign dsfp1_tx_n = eth_gty_tx_n[2*1 +: 2];
assign eth_gty_rx_p[2*1 +: 2] = dsfp1_rx_p;
assign eth_gty_rx_n[2*1 +: 2] = dsfp1_rx_n;
assign eth_gty_mgt_refclk_p[0] = dsfp_mgt_refclk_p;
assign eth_gty_mgt_refclk_n[0] = dsfp_mgt_refclk_n;
assign clk_161mhz_ref_int = eth_gty_mgt_refclk_out[0];
fpga_core #(
.SIM(SIM),
@@ -170,9 +193,9 @@ fpga_core #(
.LED_CNT(2),
.UART_CNT(UART_CNT),
.PORT_CNT(PORT_CNT),
.GTY_QUAD_CNT(1),
.GTY_CNT(1*4),
.GTY_CLK_CNT(1)
.GTY_QUAD_CNT(GTY_QUAD_CNT),
.GTY_CNT(GTY_CNT),
.GTY_CLK_CNT(GTY_CLK_CNT)
)
core_inst (
/*
@@ -202,13 +225,13 @@ core_inst (
/*
* Ethernet
*/
.eth_gty_tx_p({dsfp1_tx_p, dsfp0_tx_p}),
.eth_gty_tx_n({dsfp1_tx_n, dsfp0_tx_n}),
.eth_gty_rx_p({dsfp1_rx_p, dsfp0_rx_p}),
.eth_gty_rx_n({dsfp1_rx_n, dsfp0_rx_n}),
.eth_gty_mgt_refclk_p(dsfp_mgt_refclk_p),
.eth_gty_mgt_refclk_n(dsfp_mgt_refclk_n),
.eth_gty_mgt_refclk_out(dsfp_mgt_refclk),
.eth_gty_tx_p(eth_gty_tx_p),
.eth_gty_tx_n(eth_gty_tx_n),
.eth_gty_rx_p(eth_gty_rx_p),
.eth_gty_rx_n(eth_gty_rx_n),
.eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p),
.eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n),
.eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out),
.eth_port_modsell(),
.eth_port_resetl(),

14
src/eth/example/Alveo/fpga/tb/fpga_core/test_fpga_core.py
View File

@@ -49,6 +49,9 @@ class TB:
self.qsfp_sources = []
self.qsfp_sinks = []
for clk in dut.eth_gty_mgt_refclk_p:
cocotb.start_soon(Clock(clk, 6.4, units="ns").start())
for inst in dut.gty_quad:
for ch in inst.mac_inst.ch:
gt_inst = ch.ch_inst.gt.gt_inst
@@ -88,8 +91,6 @@ class TB:
dut.eth_port_modprsl.setimmediatevalue(0)
dut.eth_port_intl.setimmediatevalue(0)
cocotb.start_soon(self._run_refclk())
async def init(self):
self.dut.rst_125mhz.setimmediatevalue(0)
@@ -107,15 +108,6 @@ class TB:
for k in range(10):
await RisingEdge(self.dut.clk_125mhz)
async def _run_refclk(self):
t = Timer(3.2, 'ns')
val = 2**len(self.dut.eth_gty_mgt_refclk_p)-1
while True:
self.dut.eth_gty_mgt_refclk_p.value = val
await t
self.dut.eth_gty_mgt_refclk_p.value = 0
await t
async def mac_test(tb, source, sink):
tb.log.info("Test MAC")