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eth: Update example designs

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-10-02 16:11:07 -07:00
parent 76d4465081
commit 159c9d6241
45 changed files with 1561 additions and 1296 deletions
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69
src/eth/example/Alveo/fpga/rtl/fpga_au200.sv
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@@ -48,10 +48,10 @@ module fpga #
/*
* Ethernet: QSFP28
*/
output wire logic [3:0] qsfp0_tx_p,
output wire logic [3:0] qsfp0_tx_n,
input wire logic [3:0] qsfp0_rx_p,
input wire logic [3:0] qsfp0_rx_n,
output wire logic qsfp0_tx_p[4],
output wire logic qsfp0_tx_n[4],
input wire logic qsfp0_rx_p[4],
input wire logic qsfp0_rx_n[4],
input wire logic qsfp0_mgt_refclk_0_p,
input wire logic qsfp0_mgt_refclk_0_n,
// input wire logic qsfp0_mgt_refclk_1_p,
@@ -64,10 +64,10 @@ module fpga #
// output wire logic qsfp0_refclk_reset,
// output wire logic [1:0] qsfp0_fs,
output wire logic [3:0] qsfp1_tx_p,
output wire logic [3:0] qsfp1_tx_n,
input wire logic [3:0] qsfp1_rx_p,
input wire logic [3:0] qsfp1_rx_n,
output wire logic qsfp1_tx_p[4],
output wire logic qsfp1_tx_n[4],
input wire logic qsfp1_rx_p[4],
input wire logic qsfp1_rx_n[4],
input wire logic qsfp1_mgt_refclk_0_p,
input wire logic qsfp1_mgt_refclk_0_n,
// input wire logic qsfp1_mgt_refclk_1_p,
@@ -215,10 +215,35 @@ assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o;
assign i2c_sda_i = i2c_sda;
assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o;
wire qsfp0_mgt_refclk_0;
wire qsfp1_mgt_refclk_0;
localparam PORT_CNT = 2;
localparam GTY_QUAD_CNT = PORT_CNT;
localparam GTY_CNT = GTY_QUAD_CNT*4;
localparam GTY_CLK_CNT = GTY_QUAD_CNT;
assign clk_156mhz_ref_int = qsfp0_mgt_refclk_0;
wire eth_gty_tx_p[GTY_CNT];
wire eth_gty_tx_n[GTY_CNT];
wire eth_gty_rx_p[GTY_CNT];
wire eth_gty_rx_n[GTY_CNT];
wire eth_gty_mgt_refclk_p[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_n[GTY_CLK_CNT];
wire eth_gty_mgt_refclk_out[GTY_CLK_CNT];
assign qsfp0_tx_p = eth_gty_tx_p[4*0 +: 4];
assign qsfp0_tx_n = eth_gty_tx_n[4*0 +: 4];
assign eth_gty_rx_p[4*0 +: 4] = qsfp0_rx_p;
assign eth_gty_rx_n[4*0 +: 4] = qsfp0_rx_n;
assign qsfp1_tx_p = eth_gty_tx_p[4*1 +: 4];
assign qsfp1_tx_n = eth_gty_tx_n[4*1 +: 4];
assign eth_gty_rx_p[4*1 +: 4] = qsfp1_rx_p;
assign eth_gty_rx_n[4*1 +: 4] = qsfp1_rx_n;
assign eth_gty_mgt_refclk_p[0] = qsfp0_mgt_refclk_0_p;
assign eth_gty_mgt_refclk_n[0] = qsfp0_mgt_refclk_0_n;
assign eth_gty_mgt_refclk_p[1] = qsfp1_mgt_refclk_0_p;
assign eth_gty_mgt_refclk_n[1] = qsfp1_mgt_refclk_0_n;
assign clk_156mhz_ref_int = eth_gty_mgt_refclk_out[0];
fpga_core #(
.SIM(SIM),
@@ -227,10 +252,10 @@ fpga_core #(
.SW_CNT(4),
.LED_CNT(3),
.UART_CNT(1),
.PORT_CNT(2),
.GTY_QUAD_CNT(2),
.GTY_CNT(2*4),
.GTY_CLK_CNT(2)
.PORT_CNT(PORT_CNT),
.GTY_QUAD_CNT(GTY_QUAD_CNT),
.GTY_CNT(GTY_CNT),
.GTY_CLK_CNT(GTY_CLK_CNT)
)
core_inst (
/*
@@ -260,13 +285,13 @@ core_inst (
/*
* Ethernet
*/
.eth_gty_tx_p({qsfp1_tx_p, qsfp0_tx_p}),
.eth_gty_tx_n({qsfp1_tx_n, qsfp0_tx_n}),
.eth_gty_rx_p({qsfp1_rx_p, qsfp0_rx_p}),
.eth_gty_rx_n({qsfp1_rx_n, qsfp0_rx_n}),
.eth_gty_mgt_refclk_p({qsfp1_mgt_refclk_0_p, qsfp0_mgt_refclk_0_p}),
.eth_gty_mgt_refclk_n({qsfp1_mgt_refclk_0_n, qsfp0_mgt_refclk_0_n}),
.eth_gty_mgt_refclk_out({qsfp1_mgt_refclk_0, qsfp0_mgt_refclk_0}),
.eth_gty_tx_p(eth_gty_tx_p),
.eth_gty_tx_n(eth_gty_tx_n),
.eth_gty_rx_p(eth_gty_rx_p),
.eth_gty_rx_n(eth_gty_rx_n),
.eth_gty_mgt_refclk_p(eth_gty_mgt_refclk_p),
.eth_gty_mgt_refclk_n(eth_gty_mgt_refclk_n),
.eth_gty_mgt_refclk_out(eth_gty_mgt_refclk_out),
.eth_port_modsell({qsfp1_modsell, qsfp0_modsell}),
.eth_port_resetl({qsfp1_resetl, qsfp0_resetl}),