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eth: Update example designs

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-10-02 16:11:07 -07:00
parent 76d4465081
commit 159c9d6241
45 changed files with 1561 additions and 1296 deletions
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8
src/eth/example/HTG_ZRF8/fpga/rtl/fpga_r2.sv
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@@ -77,10 +77,10 @@ module fpga #
output wire logic fmc_qsfp_resetl,
output wire logic fmc_qsfp_lpmode,
output wire logic [7:0] fmc_dp_c2m_p,
output wire logic [7:0] fmc_dp_c2m_n,
input wire logic [7:0] fmc_dp_m2c_p,
input wire logic [7:0] fmc_dp_m2c_n,
output wire logic fmc_dp_c2m_p[8],
output wire logic fmc_dp_c2m_n[8],
input wire logic fmc_dp_m2c_p[8],
input wire logic fmc_dp_m2c_n[8],
input wire logic fmc_mgt_refclk_0_0_p,
input wire logic fmc_mgt_refclk_0_0_n,
input wire logic fmc_mgt_refclk_1_0_p,