mirror of
https://github.com/fpganinja/taxi.git
synced 2025-12-07 16:28:40 -08:00
eth: Support 32-bit mode in UltraScale wrapper
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
@@ -2,6 +2,8 @@ taxi_eth_mac_25g_us.sv
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taxi_eth_mac_25g_us_ch.sv
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taxi_eth_phy_25g_us_gt.f
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taxi_eth_phy_25g_us_gt_ll.f
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taxi_eth_phy_10g_us_gt.f
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taxi_eth_phy_10g_us_gt_ll.f
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../taxi_eth_mac_phy_10g.f
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../taxi_eth_mac_10g.f
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../taxi_eth_phy_10g.f
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@@ -297,7 +297,7 @@ wire [HDR_W-1:0] serdes_rx_hdr;
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wire serdes_rx_hdr_valid;
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wire serdes_rx_bitslip;
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if (CFG_LOW_LATENCY) begin : gt
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if (DATA_W == 64 && CFG_LOW_LATENCY) begin : gt
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taxi_eth_phy_25g_us_gt_ll #(
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.SIM(SIM),
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@@ -406,7 +406,7 @@ if (CFG_LOW_LATENCY) begin : gt
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.serdes_rx_bitslip(serdes_rx_bitslip)
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);
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end else begin : gt
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end else if (DATA_W == 64 && !CFG_LOW_LATENCY) begin : gt
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taxi_eth_phy_25g_us_gt #(
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.SIM(SIM),
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@@ -515,6 +515,228 @@ end else begin : gt
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.serdes_rx_bitslip(serdes_rx_bitslip)
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);
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end else if (DATA_W == 32 && CFG_LOW_LATENCY) begin : gt
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taxi_eth_phy_10g_us_gt_ll #(
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.SIM(SIM),
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.VENDOR(VENDOR),
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.FAMILY(FAMILY),
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.HAS_COMMON(HAS_COMMON),
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// GT type
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.GT_TYPE(GT_TYPE),
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// PLL parameters
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.QPLL0_PD(QPLL0_PD),
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.QPLL1_PD(QPLL1_PD),
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.QPLL0_EXT_CTRL(QPLL0_EXT_CTRL),
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.QPLL1_EXT_CTRL(QPLL1_EXT_CTRL),
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// GT parameters
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.GT_TX_PD(GT_TX_PD),
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.GT_TX_QPLL_SEL(GT_TX_QPLL_SEL),
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.GT_TX_POLARITY(GT_TX_POLARITY),
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.GT_TX_ELECIDLE(GT_TX_ELECIDLE),
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.GT_TX_INHIBIT(GT_TX_INHIBIT),
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.GT_TX_DIFFCTRL(GT_TX_DIFFCTRL),
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.GT_TX_MAINCURSOR(GT_TX_MAINCURSOR),
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.GT_TX_POSTCURSOR(GT_TX_POSTCURSOR),
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.GT_TX_PRECURSOR(GT_TX_PRECURSOR),
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.GT_RX_PD(GT_RX_PD),
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.GT_RX_QPLL_SEL(GT_RX_QPLL_SEL),
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.GT_RX_LPM_EN(GT_RX_LPM_EN),
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.GT_RX_POLARITY(GT_RX_POLARITY),
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// MAC/PHY parameters
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.DATA_W(DATA_W),
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.HDR_W(HDR_W)
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)
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gt_inst (
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.xcvr_ctrl_clk(xcvr_ctrl_clk),
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.xcvr_ctrl_rst(xcvr_ctrl_rst),
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/*
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* Common
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*/
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.xcvr_gtpowergood_out(xcvr_gtpowergood_out),
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/*
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* PLL out
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*/
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.xcvr_gtrefclk00_in(xcvr_gtrefclk00_in),
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.xcvr_qpll0pd_in(xcvr_qpll0pd_in),
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.xcvr_qpll0reset_in(xcvr_qpll0reset_in),
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.xcvr_qpll0pcierate_in(xcvr_qpll0pcierate_in),
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.xcvr_qpll0lock_out(xcvr_qpll0lock_out),
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.xcvr_qpll0clk_out(xcvr_qpll0clk_out),
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.xcvr_qpll0refclk_out(xcvr_qpll0refclk_out),
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.xcvr_gtrefclk01_in(xcvr_gtrefclk01_in),
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.xcvr_qpll1pd_in(xcvr_qpll1pd_in),
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.xcvr_qpll1reset_in(xcvr_qpll1reset_in),
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.xcvr_qpll1pcierate_in(xcvr_qpll1pcierate_in),
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.xcvr_qpll1lock_out(xcvr_qpll1lock_out),
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.xcvr_qpll1clk_out(xcvr_qpll1clk_out),
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.xcvr_qpll1refclk_out(xcvr_qpll1refclk_out),
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/*
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* PLL in
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*/
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.xcvr_qpll0lock_in(xcvr_qpll0lock_in),
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.xcvr_qpll0clk_in(xcvr_qpll0clk_in),
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.xcvr_qpll0refclk_in(xcvr_qpll0refclk_in),
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.xcvr_qpll1lock_in(xcvr_qpll1lock_in),
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.xcvr_qpll1clk_in(xcvr_qpll1clk_in),
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.xcvr_qpll1refclk_in(xcvr_qpll1refclk_in),
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/*
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* Serial data
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*/
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.xcvr_txp(xcvr_txp),
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.xcvr_txn(xcvr_txn),
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.xcvr_rxp(xcvr_rxp),
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.xcvr_rxn(xcvr_rxn),
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/*
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* GT user clocks
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*/
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.rx_clk(rx_clk),
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.rx_rst_in(rx_rst_in || rx_reset_req),
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.rx_rst_out(rx_rst_out),
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.tx_clk(tx_clk),
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.tx_rst_in(tx_rst_in),
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.tx_rst_out(tx_rst_out),
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/*
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* Serdes interface
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*/
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.serdes_tx_data(serdes_tx_data),
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.serdes_tx_data_valid(serdes_tx_data_valid),
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.serdes_tx_hdr(serdes_tx_hdr),
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.serdes_tx_hdr_valid(serdes_tx_hdr_valid),
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.serdes_tx_gbx_req_sync(serdes_tx_gbx_req_sync),
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.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
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.serdes_tx_gbx_sync(serdes_tx_gbx_sync),
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.serdes_rx_data(serdes_rx_data),
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.serdes_rx_data_valid(serdes_rx_data_valid),
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.serdes_rx_hdr(serdes_rx_hdr),
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.serdes_rx_hdr_valid(serdes_rx_hdr_valid),
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.serdes_rx_bitslip(serdes_rx_bitslip)
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);
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end else if (DATA_W == 32 && !CFG_LOW_LATENCY) begin : gt
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taxi_eth_phy_10g_us_gt #(
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.SIM(SIM),
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.VENDOR(VENDOR),
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.FAMILY(FAMILY),
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.HAS_COMMON(HAS_COMMON),
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// GT type
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.GT_TYPE(GT_TYPE),
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// PLL parameters
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.QPLL0_PD(QPLL0_PD),
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.QPLL1_PD(QPLL1_PD),
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.QPLL0_EXT_CTRL(QPLL0_EXT_CTRL),
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.QPLL1_EXT_CTRL(QPLL1_EXT_CTRL),
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// GT parameters
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.GT_TX_PD(GT_TX_PD),
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.GT_TX_QPLL_SEL(GT_TX_QPLL_SEL),
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.GT_TX_POLARITY(GT_TX_POLARITY),
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.GT_TX_ELECIDLE(GT_TX_ELECIDLE),
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.GT_TX_INHIBIT(GT_TX_INHIBIT),
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.GT_TX_DIFFCTRL(GT_TX_DIFFCTRL),
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.GT_TX_MAINCURSOR(GT_TX_MAINCURSOR),
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.GT_TX_POSTCURSOR(GT_TX_POSTCURSOR),
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.GT_TX_PRECURSOR(GT_TX_PRECURSOR),
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.GT_RX_PD(GT_RX_PD),
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.GT_RX_QPLL_SEL(GT_RX_QPLL_SEL),
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.GT_RX_LPM_EN(GT_RX_LPM_EN),
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.GT_RX_POLARITY(GT_RX_POLARITY),
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// MAC/PHY parameters
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.DATA_W(DATA_W),
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.HDR_W(HDR_W)
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)
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gt_inst (
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.xcvr_ctrl_clk(xcvr_ctrl_clk),
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.xcvr_ctrl_rst(xcvr_ctrl_rst),
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/*
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* Common
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*/
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.xcvr_gtpowergood_out(xcvr_gtpowergood_out),
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/*
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* PLL out
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*/
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.xcvr_gtrefclk00_in(xcvr_gtrefclk00_in),
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.xcvr_qpll0pd_in(xcvr_qpll0pd_in),
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.xcvr_qpll0reset_in(xcvr_qpll0reset_in),
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.xcvr_qpll0pcierate_in(xcvr_qpll0pcierate_in),
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.xcvr_qpll0lock_out(xcvr_qpll0lock_out),
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.xcvr_qpll0clk_out(xcvr_qpll0clk_out),
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.xcvr_qpll0refclk_out(xcvr_qpll0refclk_out),
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.xcvr_gtrefclk01_in(xcvr_gtrefclk01_in),
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.xcvr_qpll1pd_in(xcvr_qpll1pd_in),
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.xcvr_qpll1reset_in(xcvr_qpll1reset_in),
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.xcvr_qpll1pcierate_in(xcvr_qpll1pcierate_in),
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.xcvr_qpll1lock_out(xcvr_qpll1lock_out),
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.xcvr_qpll1clk_out(xcvr_qpll1clk_out),
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.xcvr_qpll1refclk_out(xcvr_qpll1refclk_out),
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/*
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* PLL in
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*/
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.xcvr_qpll0lock_in(xcvr_qpll0lock_in),
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.xcvr_qpll0clk_in(xcvr_qpll0clk_in),
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.xcvr_qpll0refclk_in(xcvr_qpll0refclk_in),
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.xcvr_qpll1lock_in(xcvr_qpll1lock_in),
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.xcvr_qpll1clk_in(xcvr_qpll1clk_in),
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.xcvr_qpll1refclk_in(xcvr_qpll1refclk_in),
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/*
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* Serial data
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*/
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.xcvr_txp(xcvr_txp),
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.xcvr_txn(xcvr_txn),
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.xcvr_rxp(xcvr_rxp),
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.xcvr_rxn(xcvr_rxn),
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/*
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* GT user clocks
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*/
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.rx_clk(rx_clk),
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.rx_rst_in(rx_rst_in || rx_reset_req),
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.rx_rst_out(rx_rst_out),
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.tx_clk(tx_clk),
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.tx_rst_in(tx_rst_in),
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.tx_rst_out(tx_rst_out),
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/*
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* Serdes interface
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*/
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.serdes_tx_data(serdes_tx_data),
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.serdes_tx_data_valid(serdes_tx_data_valid),
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.serdes_tx_hdr(serdes_tx_hdr),
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.serdes_tx_hdr_valid(serdes_tx_hdr_valid),
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.serdes_tx_gbx_req_sync(serdes_tx_gbx_req_sync),
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.serdes_tx_gbx_req_stall(serdes_tx_gbx_req_stall),
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.serdes_tx_gbx_sync(serdes_tx_gbx_sync),
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.serdes_rx_data(serdes_rx_data),
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.serdes_rx_data_valid(serdes_rx_data_valid),
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.serdes_rx_hdr(serdes_rx_hdr),
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.serdes_rx_hdr_valid(serdes_rx_hdr_valid),
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.serdes_rx_bitslip(serdes_rx_bitslip)
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);
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end else begin
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$fatal(0, "Error: invalid configuration (%m)");
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end
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if (COMBINED_MAC_PCS) begin : mac
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6
src/eth/rtl/us/taxi_eth_phy_10g_us_gt.f
Normal file
6
src/eth/rtl/us/taxi_eth_phy_10g_us_gt.f
Normal file
@@ -0,0 +1,6 @@
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taxi_eth_phy_10g_us_gt.sv
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../../lib/taxi/src/sync/rtl/taxi_sync_reset.sv
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../../lib/taxi/src/sync/rtl/taxi_sync_signal.sv
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../../lib/taxi/src/hip/rtl/us/taxi_gt_qpll_reset.sv
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../../lib/taxi/src/hip/rtl/us/taxi_gt_rx_reset.sv
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../../lib/taxi/src/hip/rtl/us/taxi_gt_tx_reset.sv
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1006
src/eth/rtl/us/taxi_eth_phy_10g_us_gt.sv
Normal file
1006
src/eth/rtl/us/taxi_eth_phy_10g_us_gt.sv
Normal file
File diff suppressed because it is too large
Load Diff
6
src/eth/rtl/us/taxi_eth_phy_10g_us_gt_ll.f
Normal file
6
src/eth/rtl/us/taxi_eth_phy_10g_us_gt_ll.f
Normal file
@@ -0,0 +1,6 @@
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taxi_eth_phy_10g_us_gt_ll.sv
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../../lib/taxi/src/sync/rtl/taxi_sync_reset.sv
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../../lib/taxi/src/sync/rtl/taxi_sync_signal.sv
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../../lib/taxi/src/hip/rtl/us/taxi_gt_qpll_reset.sv
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../../lib/taxi/src/hip/rtl/us/taxi_gt_rx_reset.sv
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../../lib/taxi/src/hip/rtl/us/taxi_gt_tx_reset.sv
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1090
src/eth/rtl/us/taxi_eth_phy_10g_us_gt_ll.sv
Normal file
1090
src/eth/rtl/us/taxi_eth_phy_10g_us_gt_ll.sv
Normal file
File diff suppressed because it is too large
Load Diff
132
src/eth/rtl/us/taxi_eth_phy_10g_us_gth_156.tcl
Normal file
132
src/eth/rtl/us/taxi_eth_phy_10g_us_gth_156.tcl
Normal file
@@ -0,0 +1,132 @@
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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#
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# Copyright (c) 2025 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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#
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set base_name {taxi_eth_phy_10g_us_gth}
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set preset {GTH-10GBASE-R}
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set freerun_freq {125}
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set line_rate {10.3125}
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set refclk_freq {156.25}
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set sec_line_rate {0}
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set sec_refclk_freq $refclk_freq
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set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
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set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}]
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set user_data_width {32}
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set int_data_width $user_data_width
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set rx_eq_mode {DFE}
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set extra_ports [list]
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set extra_pll_ports [list]
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# PLL reset and power down
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lappend extra_pll_ports qpll0reset_in qpll1reset_in
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lappend extra_pll_ports qpll0pd_in qpll1pd_in
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# PLL clocking
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lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
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lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
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# PCIe
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if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} {
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lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
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} else {
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lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
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}
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# channel reset
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lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txprogdivreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
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lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxprogdivreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
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# channel power down
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lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
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# channel clock selection
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lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in
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# channel polarity
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lappend extra_ports txpolarity_in rxpolarity_in
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# channel TX driver
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lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in
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# channel CDR
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lappend extra_ports rxcdrlock_out rxcdrhold_in rxcdrovrden_in
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# channel EQ
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lappend extra_ports rxlpmen_in
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set config [dict create]
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dict set config TX_LINE_RATE $line_rate
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dict set config TX_REFCLK_FREQUENCY $refclk_freq
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dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn
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dict set config TX_USER_DATA_WIDTH $user_data_width
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dict set config TX_INT_DATA_WIDTH $int_data_width
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dict set config RX_LINE_RATE $line_rate
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dict set config RX_REFCLK_FREQUENCY $refclk_freq
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dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn
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dict set config RX_USER_DATA_WIDTH $user_data_width
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dict set config RX_INT_DATA_WIDTH $int_data_width
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dict set config RX_EQ_MODE $rx_eq_mode
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if {$sec_line_rate != 0} {
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dict set config SECONDARY_QPLL_ENABLE true
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dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
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dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
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dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq
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} else {
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dict set config SECONDARY_QPLL_ENABLE false
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}
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dict set config ENABLE_OPTIONAL_PORTS $extra_ports
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dict set config LOCATE_COMMON {CORE}
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dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
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dict set config LOCATE_TX_USER_CLOCKING {CORE}
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dict set config LOCATE_RX_USER_CLOCKING {CORE}
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dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE}
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dict set config FREERUN_FREQUENCY $freerun_freq
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dict set config DISABLE_LOC_XDC {1}
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proc create_gtwizard_ip {name preset config} {
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create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name
|
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set ip [get_ips $name]
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set_property CONFIG.preset $preset $ip
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set config_list {}
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dict for {name value} $config {
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lappend config_list "CONFIG.${name}" $value
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}
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set_property -dict $config_list $ip
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}
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|
||||
# normal latency (async gearbox)
|
||||
dict set config TX_DATA_ENCODING {64B66B_ASYNC}
|
||||
dict set config TX_BUFFER_MODE {1}
|
||||
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
|
||||
dict set config RX_DATA_DECODING {64B66B_ASYNC}
|
||||
dict set config RX_BUFFER_MODE {1}
|
||||
dict set config RX_OUTCLK_SOURCE {RXPROGDIVCLK}
|
||||
|
||||
# variant with channel and common
|
||||
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
|
||||
create_gtwizard_ip "${base_name}_full" $preset $config
|
||||
|
||||
# variant with channel only
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
|
||||
|
||||
create_gtwizard_ip "${base_name}_ch" $preset $config
|
||||
|
||||
# low latency (async gearbox with buffer bypass)
|
||||
dict set config TX_DATA_ENCODING {64B66B}
|
||||
dict set config TX_BUFFER_MODE {0}
|
||||
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
|
||||
dict set config RX_DATA_DECODING {64B66B}
|
||||
dict set config RX_BUFFER_MODE {0}
|
||||
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
|
||||
|
||||
# variant with channel and common
|
||||
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
|
||||
create_gtwizard_ip "${base_name}_ll_full" $preset $config
|
||||
|
||||
# variant with channel only
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
|
||||
|
||||
create_gtwizard_ip "${base_name}_ll_ch" $preset $config
|
||||
132
src/eth/rtl/us/taxi_eth_phy_10g_us_gth_161.tcl
Normal file
132
src/eth/rtl/us/taxi_eth_phy_10g_us_gth_161.tcl
Normal file
@@ -0,0 +1,132 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
set base_name {taxi_eth_phy_10g_us_gth}
|
||||
|
||||
set preset {GTH-10GBASE-R}
|
||||
|
||||
set freerun_freq {125}
|
||||
set line_rate {10.3125}
|
||||
set refclk_freq {161.1328125}
|
||||
set sec_line_rate {0}
|
||||
set sec_refclk_freq $refclk_freq
|
||||
set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
|
||||
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}]
|
||||
set user_data_width {32}
|
||||
set int_data_width $user_data_width
|
||||
set rx_eq_mode {DFE}
|
||||
set extra_ports [list]
|
||||
set extra_pll_ports [list]
|
||||
# PLL reset and power down
|
||||
lappend extra_pll_ports qpll0reset_in qpll1reset_in
|
||||
lappend extra_pll_ports qpll0pd_in qpll1pd_in
|
||||
# PLL clocking
|
||||
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
|
||||
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
|
||||
# PCIe
|
||||
if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} {
|
||||
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
|
||||
} else {
|
||||
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
|
||||
}
|
||||
# channel reset
|
||||
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txprogdivreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
|
||||
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxprogdivreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
|
||||
# channel power down
|
||||
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
|
||||
# channel clock selection
|
||||
lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in
|
||||
# channel polarity
|
||||
lappend extra_ports txpolarity_in rxpolarity_in
|
||||
# channel TX driver
|
||||
lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in
|
||||
# channel CDR
|
||||
lappend extra_ports rxcdrlock_out rxcdrhold_in rxcdrovrden_in
|
||||
# channel EQ
|
||||
lappend extra_ports rxlpmen_in
|
||||
|
||||
set config [dict create]
|
||||
|
||||
dict set config TX_LINE_RATE $line_rate
|
||||
dict set config TX_REFCLK_FREQUENCY $refclk_freq
|
||||
dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn
|
||||
dict set config TX_USER_DATA_WIDTH $user_data_width
|
||||
dict set config TX_INT_DATA_WIDTH $int_data_width
|
||||
dict set config RX_LINE_RATE $line_rate
|
||||
dict set config RX_REFCLK_FREQUENCY $refclk_freq
|
||||
dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn
|
||||
dict set config RX_USER_DATA_WIDTH $user_data_width
|
||||
dict set config RX_INT_DATA_WIDTH $int_data_width
|
||||
dict set config RX_EQ_MODE $rx_eq_mode
|
||||
if {$sec_line_rate != 0} {
|
||||
dict set config SECONDARY_QPLL_ENABLE true
|
||||
dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
|
||||
dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
|
||||
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq
|
||||
} else {
|
||||
dict set config SECONDARY_QPLL_ENABLE false
|
||||
}
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
|
||||
dict set config LOCATE_TX_USER_CLOCKING {CORE}
|
||||
dict set config LOCATE_RX_USER_CLOCKING {CORE}
|
||||
dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE}
|
||||
dict set config FREERUN_FREQUENCY $freerun_freq
|
||||
dict set config DISABLE_LOC_XDC {1}
|
||||
|
||||
proc create_gtwizard_ip {name preset config} {
|
||||
create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name
|
||||
set ip [get_ips $name]
|
||||
set_property CONFIG.preset $preset $ip
|
||||
set config_list {}
|
||||
dict for {name value} $config {
|
||||
lappend config_list "CONFIG.${name}" $value
|
||||
}
|
||||
set_property -dict $config_list $ip
|
||||
}
|
||||
|
||||
# normal latency (async gearbox)
|
||||
dict set config TX_DATA_ENCODING {64B66B_ASYNC}
|
||||
dict set config TX_BUFFER_MODE {1}
|
||||
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
|
||||
dict set config RX_DATA_DECODING {64B66B_ASYNC}
|
||||
dict set config RX_BUFFER_MODE {1}
|
||||
dict set config RX_OUTCLK_SOURCE {RXPROGDIVCLK}
|
||||
|
||||
# variant with channel and common
|
||||
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
|
||||
create_gtwizard_ip "${base_name}_full" $preset $config
|
||||
|
||||
# variant with channel only
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
|
||||
|
||||
create_gtwizard_ip "${base_name}_ch" $preset $config
|
||||
|
||||
# low latency (async gearbox with buffer bypass)
|
||||
dict set config TX_DATA_ENCODING {64B66B}
|
||||
dict set config TX_BUFFER_MODE {0}
|
||||
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
|
||||
dict set config RX_DATA_DECODING {64B66B}
|
||||
dict set config RX_BUFFER_MODE {0}
|
||||
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
|
||||
|
||||
# variant with channel and common
|
||||
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
|
||||
create_gtwizard_ip "${base_name}_ll_full" $preset $config
|
||||
|
||||
# variant with channel only
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
|
||||
|
||||
create_gtwizard_ip "${base_name}_ll_ch" $preset $config
|
||||
132
src/eth/rtl/us/taxi_eth_phy_10g_us_gth_322.tcl
Normal file
132
src/eth/rtl/us/taxi_eth_phy_10g_us_gth_322.tcl
Normal file
@@ -0,0 +1,132 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
set base_name {taxi_eth_phy_10g_us_gth}
|
||||
|
||||
set preset {GTH-10GBASE-R}
|
||||
|
||||
set freerun_freq {125}
|
||||
set line_rate {10.3125}
|
||||
set refclk_freq {322.265625}
|
||||
set sec_line_rate {0}
|
||||
set sec_refclk_freq $refclk_freq
|
||||
set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
|
||||
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}]
|
||||
set user_data_width {32}
|
||||
set int_data_width $user_data_width
|
||||
set rx_eq_mode {DFE}
|
||||
set extra_ports [list]
|
||||
set extra_pll_ports [list]
|
||||
# PLL reset and power down
|
||||
lappend extra_pll_ports qpll0reset_in qpll1reset_in
|
||||
lappend extra_pll_ports qpll0pd_in qpll1pd_in
|
||||
# PLL clocking
|
||||
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
|
||||
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
|
||||
# PCIe
|
||||
if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} {
|
||||
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
|
||||
} else {
|
||||
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
|
||||
}
|
||||
# channel reset
|
||||
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txprogdivreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
|
||||
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxprogdivreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
|
||||
# channel power down
|
||||
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
|
||||
# channel clock selection
|
||||
lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in
|
||||
# channel polarity
|
||||
lappend extra_ports txpolarity_in rxpolarity_in
|
||||
# channel TX driver
|
||||
lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in
|
||||
# channel CDR
|
||||
lappend extra_ports rxcdrlock_out rxcdrhold_in rxcdrovrden_in
|
||||
# channel EQ
|
||||
lappend extra_ports rxlpmen_in
|
||||
|
||||
set config [dict create]
|
||||
|
||||
dict set config TX_LINE_RATE $line_rate
|
||||
dict set config TX_REFCLK_FREQUENCY $refclk_freq
|
||||
dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn
|
||||
dict set config TX_USER_DATA_WIDTH $user_data_width
|
||||
dict set config TX_INT_DATA_WIDTH $int_data_width
|
||||
dict set config RX_LINE_RATE $line_rate
|
||||
dict set config RX_REFCLK_FREQUENCY $refclk_freq
|
||||
dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn
|
||||
dict set config RX_USER_DATA_WIDTH $user_data_width
|
||||
dict set config RX_INT_DATA_WIDTH $int_data_width
|
||||
dict set config RX_EQ_MODE $rx_eq_mode
|
||||
if {$sec_line_rate != 0} {
|
||||
dict set config SECONDARY_QPLL_ENABLE true
|
||||
dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
|
||||
dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
|
||||
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq
|
||||
} else {
|
||||
dict set config SECONDARY_QPLL_ENABLE false
|
||||
}
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
|
||||
dict set config LOCATE_TX_USER_CLOCKING {CORE}
|
||||
dict set config LOCATE_RX_USER_CLOCKING {CORE}
|
||||
dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE}
|
||||
dict set config FREERUN_FREQUENCY $freerun_freq
|
||||
dict set config DISABLE_LOC_XDC {1}
|
||||
|
||||
proc create_gtwizard_ip {name preset config} {
|
||||
create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name
|
||||
set ip [get_ips $name]
|
||||
set_property CONFIG.preset $preset $ip
|
||||
set config_list {}
|
||||
dict for {name value} $config {
|
||||
lappend config_list "CONFIG.${name}" $value
|
||||
}
|
||||
set_property -dict $config_list $ip
|
||||
}
|
||||
|
||||
# normal latency (async gearbox)
|
||||
dict set config TX_DATA_ENCODING {64B66B_ASYNC}
|
||||
dict set config TX_BUFFER_MODE {1}
|
||||
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
|
||||
dict set config RX_DATA_DECODING {64B66B_ASYNC}
|
||||
dict set config RX_BUFFER_MODE {1}
|
||||
dict set config RX_OUTCLK_SOURCE {RXPROGDIVCLK}
|
||||
|
||||
# variant with channel and common
|
||||
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
|
||||
create_gtwizard_ip "${base_name}_full" $preset $config
|
||||
|
||||
# variant with channel only
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
|
||||
|
||||
create_gtwizard_ip "${base_name}_ch" $preset $config
|
||||
|
||||
# low latency (async gearbox with buffer bypass)
|
||||
dict set config TX_DATA_ENCODING {64B66B}
|
||||
dict set config TX_BUFFER_MODE {0}
|
||||
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
|
||||
dict set config RX_DATA_DECODING {64B66B}
|
||||
dict set config RX_BUFFER_MODE {0}
|
||||
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
|
||||
|
||||
# variant with channel and common
|
||||
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
|
||||
create_gtwizard_ip "${base_name}_ll_full" $preset $config
|
||||
|
||||
# variant with channel only
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
|
||||
|
||||
create_gtwizard_ip "${base_name}_ll_ch" $preset $config
|
||||
132
src/eth/rtl/us/taxi_eth_phy_10g_us_gty_156.tcl
Normal file
132
src/eth/rtl/us/taxi_eth_phy_10g_us_gty_156.tcl
Normal file
@@ -0,0 +1,132 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
set base_name {taxi_eth_phy_10g_us_gty}
|
||||
|
||||
set preset {GTY-10GBASE-R}
|
||||
|
||||
set freerun_freq {125}
|
||||
set line_rate {10.3125}
|
||||
set refclk_freq {156.25}
|
||||
set sec_line_rate {0}
|
||||
set sec_refclk_freq $refclk_freq
|
||||
set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
|
||||
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}]
|
||||
set user_data_width {32}
|
||||
set int_data_width $user_data_width
|
||||
set rx_eq_mode {DFE}
|
||||
set extra_ports [list]
|
||||
set extra_pll_ports [list]
|
||||
# PLL reset and power down
|
||||
lappend extra_pll_ports qpll0reset_in qpll1reset_in
|
||||
lappend extra_pll_ports qpll0pd_in qpll1pd_in
|
||||
# PLL clocking
|
||||
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
|
||||
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
|
||||
# PCIe
|
||||
if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} {
|
||||
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
|
||||
} else {
|
||||
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
|
||||
}
|
||||
# channel reset
|
||||
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txprogdivreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
|
||||
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxprogdivreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
|
||||
# channel power down
|
||||
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
|
||||
# channel clock selection
|
||||
lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in
|
||||
# channel polarity
|
||||
lappend extra_ports txpolarity_in rxpolarity_in
|
||||
# channel TX driver
|
||||
lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in
|
||||
# channel CDR
|
||||
lappend extra_ports rxcdrlock_out rxcdrhold_in rxcdrovrden_in
|
||||
# channel EQ
|
||||
lappend extra_ports rxlpmen_in
|
||||
|
||||
set config [dict create]
|
||||
|
||||
dict set config TX_LINE_RATE $line_rate
|
||||
dict set config TX_REFCLK_FREQUENCY $refclk_freq
|
||||
dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn
|
||||
dict set config TX_USER_DATA_WIDTH $user_data_width
|
||||
dict set config TX_INT_DATA_WIDTH $int_data_width
|
||||
dict set config RX_LINE_RATE $line_rate
|
||||
dict set config RX_REFCLK_FREQUENCY $refclk_freq
|
||||
dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn
|
||||
dict set config RX_USER_DATA_WIDTH $user_data_width
|
||||
dict set config RX_INT_DATA_WIDTH $int_data_width
|
||||
dict set config RX_EQ_MODE $rx_eq_mode
|
||||
if {$sec_line_rate != 0} {
|
||||
dict set config SECONDARY_QPLL_ENABLE true
|
||||
dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
|
||||
dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
|
||||
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq
|
||||
} else {
|
||||
dict set config SECONDARY_QPLL_ENABLE false
|
||||
}
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
|
||||
dict set config LOCATE_TX_USER_CLOCKING {CORE}
|
||||
dict set config LOCATE_RX_USER_CLOCKING {CORE}
|
||||
dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE}
|
||||
dict set config FREERUN_FREQUENCY $freerun_freq
|
||||
dict set config DISABLE_LOC_XDC {1}
|
||||
|
||||
proc create_gtwizard_ip {name preset config} {
|
||||
create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name
|
||||
set ip [get_ips $name]
|
||||
set_property CONFIG.preset $preset $ip
|
||||
set config_list {}
|
||||
dict for {name value} $config {
|
||||
lappend config_list "CONFIG.${name}" $value
|
||||
}
|
||||
set_property -dict $config_list $ip
|
||||
}
|
||||
|
||||
# normal latency (async gearbox)
|
||||
dict set config TX_DATA_ENCODING {64B66B_ASYNC}
|
||||
dict set config TX_BUFFER_MODE {1}
|
||||
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
|
||||
dict set config RX_DATA_DECODING {64B66B_ASYNC}
|
||||
dict set config RX_BUFFER_MODE {1}
|
||||
dict set config RX_OUTCLK_SOURCE {RXPROGDIVCLK}
|
||||
|
||||
# variant with channel and common
|
||||
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
|
||||
create_gtwizard_ip "${base_name}_full" $preset $config
|
||||
|
||||
# variant with channel only
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
|
||||
|
||||
create_gtwizard_ip "${base_name}_ch" $preset $config
|
||||
|
||||
# low latency (async gearbox with buffer bypass)
|
||||
dict set config TX_DATA_ENCODING {64B66B}
|
||||
dict set config TX_BUFFER_MODE {0}
|
||||
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
|
||||
dict set config RX_DATA_DECODING {64B66B}
|
||||
dict set config RX_BUFFER_MODE {0}
|
||||
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
|
||||
|
||||
# variant with channel and common
|
||||
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
|
||||
create_gtwizard_ip "${base_name}_ll_full" $preset $config
|
||||
|
||||
# variant with channel only
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
|
||||
|
||||
create_gtwizard_ip "${base_name}_ll_ch" $preset $config
|
||||
132
src/eth/rtl/us/taxi_eth_phy_10g_us_gty_161.tcl
Normal file
132
src/eth/rtl/us/taxi_eth_phy_10g_us_gty_161.tcl
Normal file
@@ -0,0 +1,132 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
set base_name {taxi_eth_phy_10g_us_gty}
|
||||
|
||||
set preset {GTY-10GBASE-R}
|
||||
|
||||
set freerun_freq {125}
|
||||
set line_rate {10.3125}
|
||||
set refclk_freq {161.1328125}
|
||||
set sec_line_rate {0}
|
||||
set sec_refclk_freq $refclk_freq
|
||||
set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
|
||||
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}]
|
||||
set user_data_width {32}
|
||||
set int_data_width $user_data_width
|
||||
set rx_eq_mode {DFE}
|
||||
set extra_ports [list]
|
||||
set extra_pll_ports [list]
|
||||
# PLL reset and power down
|
||||
lappend extra_pll_ports qpll0reset_in qpll1reset_in
|
||||
lappend extra_pll_ports qpll0pd_in qpll1pd_in
|
||||
# PLL clocking
|
||||
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
|
||||
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
|
||||
# PCIe
|
||||
if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} {
|
||||
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
|
||||
} else {
|
||||
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
|
||||
}
|
||||
# channel reset
|
||||
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txprogdivreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
|
||||
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxprogdivreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
|
||||
# channel power down
|
||||
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
|
||||
# channel clock selection
|
||||
lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in
|
||||
# channel polarity
|
||||
lappend extra_ports txpolarity_in rxpolarity_in
|
||||
# channel TX driver
|
||||
lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in
|
||||
# channel CDR
|
||||
lappend extra_ports rxcdrlock_out rxcdrhold_in rxcdrovrden_in
|
||||
# channel EQ
|
||||
lappend extra_ports rxlpmen_in
|
||||
|
||||
set config [dict create]
|
||||
|
||||
dict set config TX_LINE_RATE $line_rate
|
||||
dict set config TX_REFCLK_FREQUENCY $refclk_freq
|
||||
dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn
|
||||
dict set config TX_USER_DATA_WIDTH $user_data_width
|
||||
dict set config TX_INT_DATA_WIDTH $int_data_width
|
||||
dict set config RX_LINE_RATE $line_rate
|
||||
dict set config RX_REFCLK_FREQUENCY $refclk_freq
|
||||
dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn
|
||||
dict set config RX_USER_DATA_WIDTH $user_data_width
|
||||
dict set config RX_INT_DATA_WIDTH $int_data_width
|
||||
dict set config RX_EQ_MODE $rx_eq_mode
|
||||
if {$sec_line_rate != 0} {
|
||||
dict set config SECONDARY_QPLL_ENABLE true
|
||||
dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
|
||||
dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
|
||||
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq
|
||||
} else {
|
||||
dict set config SECONDARY_QPLL_ENABLE false
|
||||
}
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
|
||||
dict set config LOCATE_TX_USER_CLOCKING {CORE}
|
||||
dict set config LOCATE_RX_USER_CLOCKING {CORE}
|
||||
dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE}
|
||||
dict set config FREERUN_FREQUENCY $freerun_freq
|
||||
dict set config DISABLE_LOC_XDC {1}
|
||||
|
||||
proc create_gtwizard_ip {name preset config} {
|
||||
create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name
|
||||
set ip [get_ips $name]
|
||||
set_property CONFIG.preset $preset $ip
|
||||
set config_list {}
|
||||
dict for {name value} $config {
|
||||
lappend config_list "CONFIG.${name}" $value
|
||||
}
|
||||
set_property -dict $config_list $ip
|
||||
}
|
||||
|
||||
# normal latency (async gearbox)
|
||||
dict set config TX_DATA_ENCODING {64B66B_ASYNC}
|
||||
dict set config TX_BUFFER_MODE {1}
|
||||
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
|
||||
dict set config RX_DATA_DECODING {64B66B_ASYNC}
|
||||
dict set config RX_BUFFER_MODE {1}
|
||||
dict set config RX_OUTCLK_SOURCE {RXPROGDIVCLK}
|
||||
|
||||
# variant with channel and common
|
||||
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
|
||||
create_gtwizard_ip "${base_name}_full" $preset $config
|
||||
|
||||
# variant with channel only
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
|
||||
|
||||
create_gtwizard_ip "${base_name}_ch" $preset $config
|
||||
|
||||
# low latency (async gearbox with buffer bypass)
|
||||
dict set config TX_DATA_ENCODING {64B66B}
|
||||
dict set config TX_BUFFER_MODE {0}
|
||||
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
|
||||
dict set config RX_DATA_DECODING {64B66B}
|
||||
dict set config RX_BUFFER_MODE {0}
|
||||
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
|
||||
|
||||
# variant with channel and common
|
||||
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
|
||||
create_gtwizard_ip "${base_name}_ll_full" $preset $config
|
||||
|
||||
# variant with channel only
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
|
||||
|
||||
create_gtwizard_ip "${base_name}_ll_ch" $preset $config
|
||||
132
src/eth/rtl/us/taxi_eth_phy_10g_us_gty_322.tcl
Normal file
132
src/eth/rtl/us/taxi_eth_phy_10g_us_gty_322.tcl
Normal file
@@ -0,0 +1,132 @@
|
||||
# SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
#
|
||||
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||
#
|
||||
# Authors:
|
||||
# - Alex Forencich
|
||||
#
|
||||
|
||||
set base_name {taxi_eth_phy_10g_us_gty}
|
||||
|
||||
set preset {GTY-10GBASE-R}
|
||||
|
||||
set freerun_freq {125}
|
||||
set line_rate {10.3125}
|
||||
set refclk_freq {322.265625}
|
||||
set sec_line_rate {0}
|
||||
set sec_refclk_freq $refclk_freq
|
||||
set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
|
||||
set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $sec_refclk_freq, 1)*pow(2, 24))}]
|
||||
set user_data_width {32}
|
||||
set int_data_width $user_data_width
|
||||
set rx_eq_mode {DFE}
|
||||
set extra_ports [list]
|
||||
set extra_pll_ports [list]
|
||||
# PLL reset and power down
|
||||
lappend extra_pll_ports qpll0reset_in qpll1reset_in
|
||||
lappend extra_pll_ports qpll0pd_in qpll1pd_in
|
||||
# PLL clocking
|
||||
lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
|
||||
lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
|
||||
# PCIe
|
||||
if {[string first uplus [get_property FAMILY [get_property PART [current_project]]]] != -1} {
|
||||
lappend extra_pll_ports pcierateqpll0_in pcierateqpll1_in
|
||||
} else {
|
||||
lappend extra_pll_ports qpllrsvd2_in qpllrsvd3_in
|
||||
}
|
||||
# channel reset
|
||||
lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txprogdivreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
|
||||
lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxprogdivreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
|
||||
# channel power down
|
||||
lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
|
||||
# channel clock selection
|
||||
lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in
|
||||
# channel polarity
|
||||
lappend extra_ports txpolarity_in rxpolarity_in
|
||||
# channel TX driver
|
||||
lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in
|
||||
# channel CDR
|
||||
lappend extra_ports rxcdrlock_out rxcdrhold_in rxcdrovrden_in
|
||||
# channel EQ
|
||||
lappend extra_ports rxlpmen_in
|
||||
|
||||
set config [dict create]
|
||||
|
||||
dict set config TX_LINE_RATE $line_rate
|
||||
dict set config TX_REFCLK_FREQUENCY $refclk_freq
|
||||
dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn
|
||||
dict set config TX_USER_DATA_WIDTH $user_data_width
|
||||
dict set config TX_INT_DATA_WIDTH $int_data_width
|
||||
dict set config RX_LINE_RATE $line_rate
|
||||
dict set config RX_REFCLK_FREQUENCY $refclk_freq
|
||||
dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn
|
||||
dict set config RX_USER_DATA_WIDTH $user_data_width
|
||||
dict set config RX_INT_DATA_WIDTH $int_data_width
|
||||
dict set config RX_EQ_MODE $rx_eq_mode
|
||||
if {$sec_line_rate != 0} {
|
||||
dict set config SECONDARY_QPLL_ENABLE true
|
||||
dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
|
||||
dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
|
||||
dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $sec_refclk_freq
|
||||
} else {
|
||||
dict set config SECONDARY_QPLL_ENABLE false
|
||||
}
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
|
||||
dict set config LOCATE_TX_USER_CLOCKING {CORE}
|
||||
dict set config LOCATE_RX_USER_CLOCKING {CORE}
|
||||
dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE}
|
||||
dict set config FREERUN_FREQUENCY $freerun_freq
|
||||
dict set config DISABLE_LOC_XDC {1}
|
||||
|
||||
proc create_gtwizard_ip {name preset config} {
|
||||
create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name
|
||||
set ip [get_ips $name]
|
||||
set_property CONFIG.preset $preset $ip
|
||||
set config_list {}
|
||||
dict for {name value} $config {
|
||||
lappend config_list "CONFIG.${name}" $value
|
||||
}
|
||||
set_property -dict $config_list $ip
|
||||
}
|
||||
|
||||
# normal latency (async gearbox)
|
||||
dict set config TX_DATA_ENCODING {64B66B_ASYNC}
|
||||
dict set config TX_BUFFER_MODE {1}
|
||||
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
|
||||
dict set config RX_DATA_DECODING {64B66B_ASYNC}
|
||||
dict set config RX_BUFFER_MODE {1}
|
||||
dict set config RX_OUTCLK_SOURCE {RXPROGDIVCLK}
|
||||
|
||||
# variant with channel and common
|
||||
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
|
||||
create_gtwizard_ip "${base_name}_full" $preset $config
|
||||
|
||||
# variant with channel only
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
|
||||
|
||||
create_gtwizard_ip "${base_name}_ch" $preset $config
|
||||
|
||||
# low latency (async gearbox with buffer bypass)
|
||||
dict set config TX_DATA_ENCODING {64B66B}
|
||||
dict set config TX_BUFFER_MODE {0}
|
||||
dict set config TX_OUTCLK_SOURCE {TXPROGDIVCLK}
|
||||
dict set config RX_DATA_DECODING {64B66B}
|
||||
dict set config RX_BUFFER_MODE {0}
|
||||
dict set config RX_OUTCLK_SOURCE {RXOUTCLKPMA}
|
||||
|
||||
# variant with channel and common
|
||||
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
|
||||
create_gtwizard_ip "${base_name}_ll_full" $preset $config
|
||||
|
||||
# variant with channel only
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
|
||||
|
||||
create_gtwizard_ip "${base_name}_ll_ch" $preset $config
|
||||
Reference in New Issue
Block a user