Update readme

Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-04-06 23:59:16 -07:00
parent 2ae6e22c2c
commit 1fe508a6bf

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@@ -232,6 +232,10 @@ Example designs are provided for several different FPGA boards, showcasing many
* HiTech Global HTG-ZRF8-R2 (Xilinx Zynq UltraScale+ RFSoC XCZU28DR/XCZU48DR) * HiTech Global HTG-ZRF8-R2 (Xilinx Zynq UltraScale+ RFSoC XCZU28DR/XCZU48DR)
* HiTech Global HTG-ZRF8-EM (Xilinx Zynq UltraScale+ RFSoC XCZU28DR/XCZU48DR) * HiTech Global HTG-ZRF8-EM (Xilinx Zynq UltraScale+ RFSoC XCZU28DR/XCZU48DR)
* Opal Kelley XEM8320 (Xilinx Artix UltraScale+ XCAU25P) * Opal Kelley XEM8320 (Xilinx Artix UltraScale+ XCAU25P)
* Napatech NT20E3 (Xilinx Virtex 7 XC7V330T)
* Napatech NT40E3 (Xilinx Virtex 7 XC7V330T)
* Napatech NT200A01 (Xilinx Virtex UltraScale XCVU095)
* Napatech NT200A02 (Xilinx Virtex UltraScale+ XCVU5P)
* Silicom fb2CG@KU15P (Xilinx Kintex UltraScale+ XCKU15P) * Silicom fb2CG@KU15P (Xilinx Kintex UltraScale+ XCKU15P)
* Xilinx Alveo U45N/SN1000 (Xilinx Virtex UltraScale+ XCU26) * Xilinx Alveo U45N/SN1000 (Xilinx Virtex UltraScale+ XCU26)
* Xilinx Alveo U50 (Xilinx Virtex UltraScale+ XCU50) * Xilinx Alveo U50 (Xilinx Virtex UltraScale+ XCU50)