eth: Update 10G-only example designs to use 32-bit MACs

Signed-off-by: Alex Forencich <alex@alexforencich.com>

src/eth/example/KCU105/fpga/fpga_10g/Makefile

@@ -36,7 +36,7 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
 
 # IP
 IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl
-IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl
+IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gth_156.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

src/eth/example/KCU105/fpga/rtl/fpga_core.sv

@@ -487,9 +487,9 @@ end else begin : sfp_mac
 
     wire sfp_rst;
 
-    taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_sfp_tx[2]();
+    taxi_axis_if #(.DATA_W(32), .ID_W(8)) axis_sfp_tx[2]();
     taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp_tx_cpl[2]();
-    taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_sfp_rx[2]();
+    taxi_axis_if #(.DATA_W(32), .ID_W(8)) axis_sfp_rx[2]();
 
     if (SIM) begin
 
@@ -542,6 +542,7 @@ end else begin : sfp_mac
         .GT_TYPE("GTH"),
 
         // PHY parameters
+        .DATA_W(axis_sfp_tx[0].DATA_W),
         .PADDING_EN(1'b1),
         .DIC_EN(1'b1),
         .MIN_FRAME_LEN(64),

src/eth/example/KCU105/fpga/tb/fpga_core/test_fpga_core.py

@@ -74,10 +74,10 @@ class TB:
                 gt_inst = ch.ch_inst.gt.gt_inst
 
                 if ch.ch_inst.CFG_LOW_LATENCY.value:
-                    clk = 6.206
-                    gbx_cfg = (33, [32])
+                    clk = 3.102
+                    gbx_cfg = (66, [64, 65])
                 else:
-                    clk = 6.4
+                    clk = 3.2
                     gbx_cfg = None
 
                 cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start())

src/eth/example/KR260/fpga/fpga_10g/Makefile

@@ -33,7 +33,7 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
 
 # IP
-IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl
+IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gth_156.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

src/eth/example/KR260/fpga/rtl/fpga_core.sv

@@ -353,9 +353,9 @@ end else begin : sfp_mac
 
     wire sfp_rst;
 
-    taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_sfp_tx[0:0]();
+    taxi_axis_if #(.DATA_W(32), .ID_W(8)) axis_sfp_tx[0:0]();
     taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp_tx_cpl[0:0]();
-    taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_sfp_rx[0:0]();
+    taxi_axis_if #(.DATA_W(32), .ID_W(8)) axis_sfp_rx[0:0]();
     taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) axis_sfp_stat();
 
     if (SIM) begin
@@ -409,6 +409,7 @@ end else begin : sfp_mac
         .GT_TYPE("GTH"),
 
         // PHY parameters
+        .DATA_W(axis_sfp_tx[0].DATA_W),
         .PADDING_EN(1'b1),
         .DIC_EN(1'b1),
         .MIN_FRAME_LEN(64),

src/eth/example/KR260/fpga/tb/fpga_core/test_fpga_core.py

@@ -65,10 +65,10 @@ class TB:
             gt_inst = ch.ch_inst.gt.gt_inst
 
             if ch.ch_inst.CFG_LOW_LATENCY.value:
-                clk = 6.206
-                gbx_cfg = (33, [32])
+                clk = 3.102
+                gbx_cfg = (66, [64, 65])
             else:
-                clk = 6.4
+                clk = 3.2
                 gbx_cfg = None
 
             cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start())

src/eth/example/ZCU102/fpga/fpga_10g/Makefile

@@ -35,7 +35,7 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
 
 # IP
-IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl
+IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gth_156.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

src/eth/example/ZCU102/fpga/rtl/fpga_core.sv

@@ -574,9 +574,9 @@ end else begin : sfp_mac
 
     wire sfp_rst;
 
-    taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_sfp_tx[4]();
+    taxi_axis_if #(.DATA_W(32), .ID_W(8)) axis_sfp_tx[4]();
     taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp_tx_cpl[4]();
-    taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_sfp_rx[4]();
+    taxi_axis_if #(.DATA_W(32), .ID_W(8)) axis_sfp_rx[4]();
 
     if (SIM) begin
 
@@ -629,6 +629,7 @@ end else begin : sfp_mac
         .GT_TYPE("GTH"),
 
         // PHY parameters
+        .DATA_W(axis_sfp_tx[0].DATA_W),
         .PADDING_EN(1'b1),
         .DIC_EN(1'b1),
         .MIN_FRAME_LEN(64),

src/eth/example/ZCU102/fpga/tb/fpga_core/test_fpga_core.py

@@ -80,10 +80,10 @@ class TB:
                 gt_inst = ch.ch_inst.gt.gt_inst
 
                 if ch.ch_inst.CFG_LOW_LATENCY.value:
-                    clk = 6.206
-                    gbx_cfg = (33, [32])
+                    clk = 3.102
+                    gbx_cfg = (66, [64, 65])
                 else:
-                    clk = 6.4
+                    clk = 3.2
                     gbx_cfg = None
 
                 cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start())

src/eth/example/ZCU106/fpga/fpga_10g/Makefile

@@ -35,7 +35,7 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
 
 # IP
-IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl
+IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gth_156.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

src/eth/example/ZCU106/fpga/fpga_10g/config.tcl

@@ -15,6 +15,7 @@ dict set params SFP_RATE "1"
 # 10G MAC configuration
 dict set params CFG_LOW_LATENCY "1"
 dict set params COMBINED_MAC_PCS "1"
+dict set params MAC_DATA_W "32"
 
 # apply parameters to top-level
 set param_list {}

src/eth/example/ZCU106/fpga/fpga_10g_64/Makefile

@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xczu7ev-ffvc1156-2-e
+FPGA_TOP = fpga
+FPGA_ARCH = zynquplus
+
+RTL_DIR = ../rtl
+LIB_DIR = ../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+# Files for synthesis
+SYN_FILES = $(RTL_DIR)/fpga.sv
+SYN_FILES += $(RTL_DIR)/fpga_core.sv
+SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
+SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
+
+# XDC files
+XDC_FILES = ../fpga.xdc
+XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
+
+# IP
+IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl
+
+# Configuration
+CONFIG_TCL_FILES = ./config.tcl
+
+include ../common/vivado.mk
+
+program: $(FPGA_TOP).bit
+	echo "open_hw_manager" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+

src/eth/example/ZCU106/fpga/fpga_10g_64/config.tcl

@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+set params [dict create]
+
+# SFP+ rate
+# 0 for 1G, 1 for 10G
+dict set params SFP_RATE "1"
+
+# 10G MAC configuration
+dict set params CFG_LOW_LATENCY "1"
+dict set params COMBINED_MAC_PCS "1"
+dict set params MAC_DATA_W "64"
+
+# apply parameters to top-level
+set param_list {}
+dict for {name value} $params {
+    lappend param_list $name=$value
+}
+
+set_property generic $param_list [get_filesets sources_1]

src/eth/example/ZCU106/fpga/fpga_10g_64_async/Makefile

@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xczu7ev-ffvc1156-2-e
+FPGA_TOP = fpga
+FPGA_ARCH = zynquplus
+
+RTL_DIR = ../rtl
+LIB_DIR = ../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+# Files for synthesis
+SYN_FILES = $(RTL_DIR)/fpga.sv
+SYN_FILES += $(RTL_DIR)/fpga_core.sv
+SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
+SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
+
+# XDC files
+XDC_FILES = ../fpga.xdc
+XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
+
+# IP
+IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl
+
+# Configuration
+CONFIG_TCL_FILES = ./config.tcl
+
+include ../common/vivado.mk
+
+program: $(FPGA_TOP).bit
+	echo "open_hw_manager" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+

src/eth/example/ZCU106/fpga/fpga_10g_64_async/config.tcl

@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+set params [dict create]
+
+# SFP+ rate
+# 0 for 1G, 1 for 10G
+dict set params SFP_RATE "1"
+
+# 10G MAC configuration
+dict set params CFG_LOW_LATENCY "0"
+dict set params COMBINED_MAC_PCS "1"
+dict set params MAC_DATA_W "64"
+
+# apply parameters to top-level
+set param_list {}
+dict for {name value} $params {
+    lappend param_list $name=$value
+}
+
+set_property generic $param_list [get_filesets sources_1]

src/eth/example/ZCU106/fpga/fpga_10g_64_split/Makefile

@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xczu7ev-ffvc1156-2-e
+FPGA_TOP = fpga
+FPGA_ARCH = zynquplus
+
+RTL_DIR = ../rtl
+LIB_DIR = ../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+# Files for synthesis
+SYN_FILES = $(RTL_DIR)/fpga.sv
+SYN_FILES += $(RTL_DIR)/fpga_core.sv
+SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
+SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
+
+# XDC files
+XDC_FILES = ../fpga.xdc
+XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
+
+# IP
+IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl
+
+# Configuration
+CONFIG_TCL_FILES = ./config.tcl
+
+include ../common/vivado.mk
+
+program: $(FPGA_TOP).bit
+	echo "open_hw_manager" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+

src/eth/example/ZCU106/fpga/fpga_10g_64_split/config.tcl

@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+set params [dict create]
+
+# SFP+ rate
+# 0 for 1G, 1 for 10G
+dict set params SFP_RATE "1"
+
+# 10G MAC configuration
+dict set params CFG_LOW_LATENCY "1"
+dict set params COMBINED_MAC_PCS "0"
+dict set params MAC_DATA_W "64"
+
+# apply parameters to top-level
+set param_list {}
+dict for {name value} $params {
+    lappend param_list $name=$value
+}
+
+set_property generic $param_list [get_filesets sources_1]

src/eth/example/ZCU106/fpga/fpga_10g_64_split_async/Makefile

@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+# FPGA settings
+FPGA_PART = xczu7ev-ffvc1156-2-e
+FPGA_TOP = fpga
+FPGA_ARCH = zynquplus
+
+RTL_DIR = ../rtl
+LIB_DIR = ../lib
+TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
+
+# Files for synthesis
+SYN_FILES = $(RTL_DIR)/fpga.sv
+SYN_FILES += $(RTL_DIR)/fpga_core.sv
+SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
+SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
+SYN_FILES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_async_fifo.f
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
+SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
+SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
+
+# XDC files
+XDC_FILES = ../fpga.xdc
+XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
+XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
+
+# IP
+IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl
+
+# Configuration
+CONFIG_TCL_FILES = ./config.tcl
+
+include ../common/vivado.mk
+
+program: $(FPGA_TOP).bit
+	echo "open_hw_manager" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+

src/eth/example/ZCU106/fpga/fpga_10g_64_split_async/config.tcl

@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: MIT
+#
+# Copyright (c) 2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+#
+
+set params [dict create]
+
+# SFP+ rate
+# 0 for 1G, 1 for 10G
+dict set params SFP_RATE "1"
+
+# 10G MAC configuration
+dict set params CFG_LOW_LATENCY "0"
+dict set params COMBINED_MAC_PCS "0"
+dict set params MAC_DATA_W "64"
+
+# apply parameters to top-level
+set param_list {}
+dict for {name value} $params {
+    lappend param_list $name=$value
+}
+
+set_property generic $param_list [get_filesets sources_1]

src/eth/example/ZCU106/fpga/fpga_10g_async/Makefile

@@ -35,7 +35,7 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
 
 # IP
-IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl
+IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gth_156.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

src/eth/example/ZCU106/fpga/fpga_10g_async/config.tcl

@@ -15,6 +15,7 @@ dict set params SFP_RATE "1"
 # 10G MAC configuration
 dict set params CFG_LOW_LATENCY "0"
 dict set params COMBINED_MAC_PCS "1"
+dict set params MAC_DATA_W "32"
 
 # apply parameters to top-level
 set param_list {}

src/eth/example/ZCU106/fpga/fpga_10g_split/Makefile

@@ -35,7 +35,7 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
 
 # IP
-IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl
+IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gth_156.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

src/eth/example/ZCU106/fpga/fpga_10g_split/config.tcl

@@ -15,6 +15,7 @@ dict set params SFP_RATE "1"
 # 10G MAC configuration
 dict set params CFG_LOW_LATENCY "1"
 dict set params COMBINED_MAC_PCS "0"
+dict set params MAC_DATA_W "32"
 
 # apply parameters to top-level
 set param_list {}

src/eth/example/ZCU106/fpga/fpga_10g_split_async/Makefile

@@ -35,7 +35,7 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
 XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
 
 # IP
-IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl
+IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gth_156.tcl
 
 # Configuration
 CONFIG_TCL_FILES = ./config.tcl

src/eth/example/ZCU106/fpga/fpga_10g_split_async/config.tcl

@@ -15,6 +15,7 @@ dict set params SFP_RATE "1"
 # 10G MAC configuration
 dict set params CFG_LOW_LATENCY "0"
 dict set params COMBINED_MAC_PCS "0"
+dict set params MAC_DATA_W "32"
 
 # apply parameters to top-level
 set param_list {}

src/eth/example/ZCU106/fpga/fpga_1g/config.tcl

@@ -15,6 +15,7 @@ dict set params SFP_RATE "0"
 # 10G MAC configuration
 dict set params CFG_LOW_LATENCY "1"
 dict set params COMBINED_MAC_PCS "1"
+dict set params MAC_DATA_W "32"
 
 # apply parameters to top-level
 set param_list {}

src/eth/example/ZCU106/fpga/rtl/fpga.sv

@@ -27,7 +27,8 @@ module fpga #
     parameter logic SFP_RATE = 1'b1,
     // 10G MAC configuration
     parameter logic CFG_LOW_LATENCY = 1'b1,
-    parameter logic COMBINED_MAC_PCS = 1'b1
+    parameter logic COMBINED_MAC_PCS = 1'b1,
+    parameter MAC_DATA_W = 32
 )
 (
     /*
@@ -430,7 +431,8 @@ fpga_core #(
     .FAMILY(FAMILY),
     .SFP_RATE(SFP_RATE),
     .CFG_LOW_LATENCY(CFG_LOW_LATENCY),
-    .COMBINED_MAC_PCS(COMBINED_MAC_PCS)
+    .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
+    .MAC_DATA_W(MAC_DATA_W)
 )
 core_inst (
     /*

src/eth/example/ZCU106/fpga/rtl/fpga_core.sv

@@ -27,7 +27,8 @@ module fpga_core #
     parameter logic SFP_RATE = 1'b1,
     // 10G MAC configuration
     parameter logic CFG_LOW_LATENCY = 1'b1,
-    parameter logic COMBINED_MAC_PCS = 1'b1
+    parameter logic COMBINED_MAC_PCS = 1'b1,
+    parameter MAC_DATA_W = 32
 )
 (
     /*
@@ -387,9 +388,9 @@ end else begin : sfp_mac
 
     wire sfp_rst;
 
-    taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_sfp_tx[2]();
+    taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) axis_sfp_tx[2]();
     taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_sfp_tx_cpl[2]();
-    taxi_axis_if #(.DATA_W(64), .ID_W(8)) axis_sfp_rx[2]();
+    taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8)) axis_sfp_rx[2]();
 
     if (SIM) begin
 
@@ -443,6 +444,7 @@ end else begin : sfp_mac
 
         // PHY parameters
         .COMBINED_MAC_PCS(COMBINED_MAC_PCS),
+        .DATA_W(MAC_DATA_W),
         .PADDING_EN(1'b1),
         .DIC_EN(1'b1),
         .MIN_FRAME_LEN(64),

src/eth/example/ZCU106/fpga/tb/fpga_core/Makefile

@@ -43,6 +43,9 @@ export PARAM_SIM := "1'b1"
 export PARAM_VENDOR := "\"XILINX\""
 export PARAM_FAMILY := "\"zynquplus\""
 export PARAM_SFP_RATE := "1'b1"
+export PARAM_CFG_LOW_LATENCY := "1'b1"
+export PARAM_COMBINED_MAC_PCS := "1'b1"
+export PARAM_MAC_DATA_W := "32"
 
 ifeq ($(SIM), icarus)
 	PLUSARGS += -fst

src/eth/example/ZCU106/fpga/tb/fpga_core/test_fpga_core.py

@@ -68,10 +68,10 @@ class TB:
                 gt_inst = ch.ch_inst.gt.gt_inst
 
                 if ch.ch_inst.CFG_LOW_LATENCY.value:
-                    clk = 6.206
-                    gbx_cfg = (33, [32])
+                    clk = 3.102
+                    gbx_cfg = (66, [64, 65])
                 else:
-                    clk = 6.4
+                    clk = 3.2
                     gbx_cfg = None
 
                 cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start())
@@ -289,6 +289,9 @@ def test_fpga_core(request, sfp_rate):
     parameters['VENDOR'] = "\"XILINX\""
     parameters['FAMILY'] = "\"zynquplus\""
     parameters['SFP_RATE'] = f"1'b{sfp_rate}"
+    parameters['CFG_LOW_LATENCY'] = "1'b1"
+    parameters['COMBINED_MAC_PCS'] = "1'b1"
+    parameters['MAC_DATA_W'] = 32
 
     extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}