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eth: Update 10G-only example designs to use 32-bit MACs

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-06-17 23:19:30 -07:00
parent 7031a3f0b1
commit 2065151c01
30 changed files with 372 additions and 30 deletions
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2
src/eth/example/ZCU106/fpga/fpga_10g_async/Makefile
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@@ -35,7 +35,7 @@ XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
# IP
IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gth_10g_156.tcl
IP_TCL_FILES = $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gth_156.tcl
# Configuration
CONFIG_TCL_FILES = ./config.tcl

1
src/eth/example/ZCU106/fpga/fpga_10g_async/config.tcl
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@@ -15,6 +15,7 @@ dict set params SFP_RATE "1"
# 10G MAC configuration
dict set params CFG_LOW_LATENCY "0"
dict set params COMBINED_MAC_PCS "1"
dict set params MAC_DATA_W "32"
# apply parameters to top-level
set param_list {}