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eth: Simulation speed optimization

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-06-09 20:04:02 -07:00
parent 2957a0ced9
commit 22d402ee50
2 changed files with 12 additions and 4 deletions
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8
src/eth/tb/baser.py
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@@ -205,6 +205,8 @@ class BaseRSerdesSource():
last_d = 0
self.active = False
clock_edge_event = RisingEdge(self.clock)
clk_period = 0
last_clk = 0
gbx_delay = 0
@@ -213,7 +215,7 @@ class BaseRSerdesSource():
hdr = 0
while True:
await RisingEdge(self.clock)
await clock_edge_event
sim_time = get_sim_time()
if last_clk:
@@ -648,6 +650,8 @@ class BaseRSerdesSink:
in_pre = False
self.active = False
clock_edge_event = RisingEdge(self.clock)
clk_period = 0
last_clk = 0
gbx_delay = 0
@@ -657,7 +661,7 @@ class BaseRSerdesSink:
hdr = 0
while True:
await RisingEdge(self.clock)
await clock_edge_event
sim_time = get_sim_time()
if last_clk:

8
src/eth/tb/basex.py
View File

@@ -291,6 +291,8 @@ class BaseXSerdesSource():
last_d = 0
self.active = False
clock_edge_event = RisingEdge(self.clock)
clk_period = 0
last_clk = 0
gbx_delay = 0
@@ -299,7 +301,7 @@ class BaseXSerdesSource():
data_k = 0
while True:
await RisingEdge(self.clock)
await clock_edge_event
sim_time = get_sim_time()
if last_clk:
@@ -625,6 +627,8 @@ class BaseXSerdesSink:
in_pre = False
self.active = False
clock_edge_event = RisingEdge(self.clock)
clk_period = 0
last_clk = 0
gbx_delay = 0
@@ -634,7 +638,7 @@ class BaseXSerdesSink:
data_k = 0
while True:
await RisingEdge(self.clock)
await clock_edge_event
sim_time = get_sim_time()
if last_clk: