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eth: Update CMAC wrapper clocking

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-08-08 00:35:50 -07:00
parent ded4f94a0e
commit 24ad4c970f
7 changed files with 170 additions and 96 deletions
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12
src/eth/rtl/us/taxi_eth_mac_100g_us.sv
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@@ -326,6 +326,12 @@ ctrl_intercon_inst (
localparam STAT_TX_CNT = STAT_TX_LEVEL == 0 ? 8 : (STAT_TX_LEVEL == 1 ? 16: 32);
localparam STAT_RX_CNT = STAT_RX_LEVEL == 0 ? 8 : (STAT_RX_LEVEL == 1 ? 16: 32);
wire tx_clk_out[CNT];
wire rx_clk_out[CNT];
assign tx_clk = '{CNT{tx_clk_out[0]}};
assign rx_clk = rx_clk_out;
wire [127:0] serdes_txdata[CNT];
wire [15:0] serdes_txctrl0[CNT];
wire [15:0] serdes_txctrl1[CNT];
@@ -439,10 +445,12 @@ for (genvar n = 0; n < CNT; n = n + 1) begin : ch
/*
* MAC clocks
*/
.rx_clk(rx_clk[n]),
.rx_clk_out(rx_clk_out[n]),
.rx_clk_in(rx_clk[n]),
.rx_rst_in(rx_rst_in[n]),
.rx_rst_out(rx_rst_out[n]),
.tx_clk(tx_clk[n]),
.tx_clk_out(tx_clk_out[n]),
.tx_clk_in(tx_clk[n]),
.tx_rst_in(tx_rst_in[n]),
.tx_rst_out(tx_rst_out[n]),

22
src/eth/rtl/us/taxi_eth_mac_100g_us_ch.sv
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@@ -101,10 +101,12 @@ module taxi_eth_mac_100g_us_ch #
/*
* MAC clocks
*/
output wire logic rx_clk,
output wire logic rx_clk_out,
input wire logic rx_clk_in = 1'b0,
input wire logic rx_rst_in = 1'b0,
output wire logic rx_rst_out,
output wire logic tx_clk,
output wire logic tx_clk_out,
input wire logic tx_clk_in = 1'b0,
input wire logic tx_rst_in = 1'b0,
output wire logic tx_rst_out,
@@ -137,7 +139,7 @@ if (TX_SERDES_PIPELINE > 0) begin : tx_pipe
(* shreg_extract = "no" *)
reg [15:0] serdes_txctrl1_pipe_reg[TX_SERDES_PIPELINE-1:0];
always @(posedge tx_clk) begin
always @(posedge tx_clk_in) begin
serdes_txdata_pipe_reg[0] <= serdes_txdata;
serdes_txctrl0_pipe_reg[0] <= serdes_txctrl0;
serdes_txctrl1_pipe_reg[0] <= serdes_txctrl1;
@@ -170,7 +172,7 @@ if (RX_SERDES_PIPELINE > 0) begin : rx_pipe
(* shreg_extract = "no" *)
reg [15:0] serdes_rxctrl1_pipe_reg[RX_SERDES_PIPELINE-1:0];
always @(posedge rx_clk) begin
always @(posedge rx_clk_in) begin
serdes_rxdata_pipe_reg[0] <= gt_rxdata;
serdes_rxctrl0_pipe_reg[0] <= gt_rxctrl0;
serdes_rxctrl1_pipe_reg[0] <= gt_rxctrl1;
@@ -274,10 +276,12 @@ if (CFG_LOW_LATENCY) begin : gt
/*
* GT user clocks
*/
.rx_clk(rx_clk),
.rx_clk_out(rx_clk_out),
.rx_clk_in(rx_clk_in),
.rx_rst_in(rx_rst_in || rx_reset_req),
.rx_rst_out(rx_rst_out),
.tx_clk(tx_clk),
.tx_clk_out(tx_clk_out),
.tx_clk_in(tx_clk_in),
.tx_rst_in(tx_rst_in),
.tx_rst_out(tx_rst_out),
@@ -372,10 +376,12 @@ end else if (!CFG_LOW_LATENCY) begin : gt
/*
* GT user clocks
*/
.rx_clk(rx_clk),
.rx_clk_out(rx_clk_out),
.rx_clk_in(rx_clk_in),
.rx_rst_in(rx_rst_in || rx_reset_req),
.rx_rst_out(rx_rst_out),
.tx_clk(tx_clk),
.tx_clk_out(tx_clk_out),
.tx_clk_in(tx_clk_in),
.tx_rst_in(tx_rst_in),
.tx_rst_out(tx_rst_out),

110
src/eth/rtl/us/taxi_eth_mac_100g_us_gt.sv
View File

@@ -94,10 +94,12 @@ module taxi_eth_mac_100g_us_gt #
/*
* GT user clocks
*/
output wire logic rx_clk,
output wire logic rx_clk_out,
input wire logic rx_clk_in = 1'b0,
input wire logic rx_rst_in = 1'b0,
output wire logic rx_rst_out,
output wire logic tx_clk,
output wire logic tx_clk_out,
input wire logic tx_clk_in = 1'b0,
input wire logic tx_rst_in = 1'b0,
output wire logic tx_rst_out,
@@ -214,8 +216,8 @@ ctrl_regs_inst (
/*
* Transceiver clocks
*/
.gt_txusrclk2(tx_clk),
.gt_rxusrclk2(rx_clk),
.gt_txusrclk2(tx_clk_in),
.gt_rxusrclk2(rx_clk_in),
/*
* Transceiver control
@@ -369,9 +371,13 @@ end else begin : common_ctrl
end
wire gt_txoutclk;
wire gt_rxoutclk;
wire gt_tx_pd;
wire gt_tx_reset;
wire gt_tx_reset_done;
wire gt_userclk_tx_active;
wire gt_tx_pma_reset;
wire gt_tx_pcs_reset;
wire gt_tx_pma_reset_done;
@@ -384,7 +390,7 @@ taxi_sync_reset #(
.N(4)
)
tx_reset_sync_inst (
.clk(tx_clk),
.clk(tx_clk_in),
.rst(!tx_reset_done || tx_rst_in),
.out(tx_rst_out)
);
@@ -401,11 +407,11 @@ gt_tx_reset_inst (
/*
* GT
*/
.gt_txusrclk2(tx_clk),
.gt_txusrclk2(tx_clk_in),
.gt_tx_pd_out(gt_tx_pd),
.gt_tx_reset_out(gt_tx_reset),
.gt_tx_reset_done_in(gt_tx_reset_done),
.gt_userclk_tx_active_out(),
.gt_userclk_tx_active_out(gt_userclk_tx_active),
.gt_tx_pma_reset_out(gt_tx_pma_reset),
.gt_tx_pcs_reset_out(gt_tx_pcs_reset),
.gt_tx_pma_reset_done_in(gt_tx_pma_reset_done),
@@ -432,6 +438,7 @@ gt_tx_reset_inst (
wire gt_rx_pd;
wire gt_rx_reset;
wire gt_rx_reset_done;
wire gt_userclk_rx_active;
wire gt_rx_pma_reset;
wire gt_rx_dfe_lpm_reset;
wire gt_rx_eyescan_reset;
@@ -448,7 +455,7 @@ taxi_sync_reset #(
.N(4)
)
rx_reset_sync_inst (
.clk(rx_clk),
.clk(rx_clk_in),
.rst(!rx_reset_done || rx_rst_in),
.out(rx_rst_out)
);
@@ -467,11 +474,11 @@ gt_rx_reset_inst (
/*
* GT
*/
.gt_rxusrclk2(rx_clk),
.gt_rxusrclk2(rx_clk_in),
.gt_rx_pd_out(gt_rx_pd),
.gt_rx_reset_out(gt_rx_reset),
.gt_rx_reset_done_in(gt_rx_reset_done),
.gt_userclk_rx_active_out(),
.gt_userclk_rx_active_out(gt_userclk_rx_active),
.gt_rx_pma_reset_out(gt_rx_pma_reset),
.gt_rx_dfe_lpm_reset_out(gt_rx_dfe_lpm_reset),
.gt_rx_eyescan_reset_out(gt_rx_eyescan_reset),
@@ -502,6 +509,35 @@ gt_rx_reset_inst (
.rx_lpm_en_in(ctrl_rxlpmen)
);
if (SIM) begin : clkbuf
assign tx_clk_out = gt_txoutclk;
assign rx_clk_out = gt_rxoutclk;
end else begin : clkbuf
BUFG_GT bufg_gt_txusrclk_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gt_tx_reset),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (gt_txoutclk),
.O (tx_clk_out)
);
BUFG_GT bufg_gt_rxusrclk_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gt_rx_reset),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (gt_rxoutclk),
.O (rx_clk_out)
);
end
if (SIM) begin : xcvr
// simulation (no GT core)
@@ -577,12 +613,11 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && GT_USP) begin : xcvr
.gtyrxn_in(xcvr_rxn),
// Transmit
.gtwiz_userclk_tx_reset_in(gt_tx_reset),
.gtwiz_userclk_tx_srcclk_out(),
.gtwiz_userclk_tx_usrclk_out(),
.gtwiz_userclk_tx_usrclk2_out(tx_clk),
.gtwiz_userclk_tx_active_out(),
.gtwiz_userclk_tx_active_in(gt_userclk_tx_active),
.gtwiz_reset_tx_done_in(tx_reset_done),
.txoutclk_out(gt_txoutclk),
.txusrclk_in(tx_clk_in),
.txusrclk2_in(tx_clk_in),
.txpdelecidlemode_in(1'b1),
.txpd_in(gt_tx_pd ? 2'b11 : 2'b00),
.gttxreset_in(gt_tx_reset),
@@ -609,12 +644,11 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && GT_USP) begin : xcvr
.txctrl1_in(serdes_txctrl1),
// Receive
.gtwiz_userclk_rx_reset_in(gt_rx_reset),
.gtwiz_userclk_rx_srcclk_out(),
.gtwiz_userclk_rx_usrclk_out(),
.gtwiz_userclk_rx_usrclk2_out(rx_clk),
.gtwiz_userclk_rx_active_out(),
.gtwiz_userclk_rx_active_in(gt_userclk_rx_active),
.gtwiz_reset_rx_done_in(rx_reset_done),
.rxoutclk_out(gt_rxoutclk),
.rxusrclk_in(rx_clk_in),
.rxusrclk2_in(rx_clk_in),
.rxpd_in(gt_rx_pd ? 2'b11 : 2'b00),
.gtrxreset_in(gt_rx_reset),
.rxpmareset_in(gt_rx_pma_reset),
@@ -689,12 +723,11 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && !GT_USP) begin : xcvr
.gtyrxn_in(xcvr_rxn),
// Transmit
.gtwiz_userclk_tx_reset_in(gt_tx_reset),
.gtwiz_userclk_tx_srcclk_out(),
.gtwiz_userclk_tx_usrclk_out(),
.gtwiz_userclk_tx_usrclk2_out(tx_clk),
.gtwiz_userclk_tx_active_out(),
.gtwiz_userclk_tx_active_in(gt_userclk_tx_active),
.gtwiz_reset_tx_done_in(tx_reset_done),
.txoutclk_out(gt_txoutclk),
.txusrclk_in(tx_clk_in),
.txusrclk2_in(tx_clk_in),
.txpdelecidlemode_in(1'b1),
.txpd_in(gt_tx_pd ? 2'b11 : 2'b00),
.gttxreset_in(gt_tx_reset),
@@ -721,12 +754,11 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && !GT_USP) begin : xcvr
.txctrl1_in(serdes_txctrl1),
// Receive
.gtwiz_userclk_rx_reset_in(gt_rx_reset),
.gtwiz_userclk_rx_srcclk_out(),
.gtwiz_userclk_rx_usrclk_out(),
.gtwiz_userclk_rx_usrclk2_out(rx_clk),
.gtwiz_userclk_rx_active_out(),
.gtwiz_userclk_rx_active_in(gt_userclk_rx_active),
.gtwiz_reset_rx_done_in(rx_reset_done),
.rxoutclk_out(gt_rxoutclk),
.rxusrclk_in(rx_clk_in),
.rxusrclk2_in(rx_clk_in),
.rxpd_in(gt_rx_pd ? 2'b11 : 2'b00),
.gtrxreset_in(gt_rx_reset),
.rxpmareset_in(gt_rx_pma_reset),
@@ -784,12 +816,11 @@ end else if (!HAS_COMMON && GT_TYPE == "GTY") begin : xcvr
.gtyrxn_in(xcvr_rxn),
// Transmit
.gtwiz_userclk_tx_reset_in(gt_tx_reset),
.gtwiz_userclk_tx_srcclk_out(),
.gtwiz_userclk_tx_usrclk_out(),
.gtwiz_userclk_tx_usrclk2_out(tx_clk),
.gtwiz_userclk_tx_active_out(),
.gtwiz_userclk_tx_active_in(gt_userclk_tx_active),
.gtwiz_reset_tx_done_in(tx_reset_done),
.txoutclk_out(gt_txoutclk),
.txusrclk_in(tx_clk_in),
.txusrclk2_in(tx_clk_in),
.txpdelecidlemode_in(1'b1),
.txpd_in(gt_tx_pd ? 2'b11 : 2'b00),
.gttxreset_in(gt_tx_reset),
@@ -816,12 +847,11 @@ end else if (!HAS_COMMON && GT_TYPE == "GTY") begin : xcvr
.txctrl1_in(serdes_txctrl1),
// Receive
.gtwiz_userclk_rx_reset_in(gt_rx_reset),
.gtwiz_userclk_rx_srcclk_out(),
.gtwiz_userclk_rx_usrclk_out(),
.gtwiz_userclk_rx_usrclk2_out(rx_clk),
.gtwiz_userclk_rx_active_out(),
.gtwiz_userclk_rx_active_in(gt_userclk_rx_active),
.gtwiz_reset_rx_done_in(rx_reset_done),
.rxoutclk_out(gt_rxoutclk),
.rxusrclk_in(rx_clk_in),
.rxusrclk2_in(rx_clk_in),
.rxpd_in(gt_rx_pd ? 2'b11 : 2'b00),
.gtrxreset_in(gt_rx_reset),
.rxpmareset_in(gt_rx_pma_reset),

110
src/eth/rtl/us/taxi_eth_mac_100g_us_gt_ll.sv
View File

@@ -94,10 +94,12 @@ module taxi_eth_mac_100g_us_gt_ll #
/*
* GT user clocks
*/
output wire logic rx_clk,
output wire logic rx_clk_out,
input wire logic rx_clk_in = 1'b0,
input wire logic rx_rst_in = 1'b0,
output wire logic rx_rst_out,
output wire logic tx_clk,
output wire logic tx_clk_out,
input wire logic tx_clk_in = 1'b0,
input wire logic tx_rst_in = 1'b0,
output wire logic tx_rst_out,
@@ -214,8 +216,8 @@ ctrl_regs_inst (
/*
* Transceiver clocks
*/
.gt_txusrclk2(tx_clk),
.gt_rxusrclk2(rx_clk),
.gt_txusrclk2(tx_clk_in),
.gt_rxusrclk2(rx_clk_in),
/*
* Transceiver control
@@ -369,9 +371,13 @@ end else begin : common_ctrl
end
wire gt_txoutclk;
wire gt_rxoutclk;
wire gt_tx_pd;
wire gt_tx_reset;
wire gt_tx_reset_done;
wire gt_userclk_tx_active;
wire gt_tx_pma_reset;
wire gt_tx_pcs_reset;
wire gt_tx_pma_reset_done;
@@ -384,7 +390,7 @@ taxi_sync_reset #(
.N(4)
)
tx_reset_sync_inst (
.clk(tx_clk),
.clk(tx_clk_in),
.rst(!tx_reset_done || tx_rst_in),
.out(tx_rst_out)
);
@@ -401,11 +407,11 @@ gt_tx_reset_inst (
/*
* GT
*/
.gt_txusrclk2(tx_clk),
.gt_txusrclk2(tx_clk_in),
.gt_tx_pd_out(gt_tx_pd),
.gt_tx_reset_out(gt_tx_reset),
.gt_tx_reset_done_in(gt_tx_reset_done),
.gt_userclk_tx_active_out(),
.gt_userclk_tx_active_out(gt_userclk_tx_active),
.gt_tx_pma_reset_out(gt_tx_pma_reset),
.gt_tx_pcs_reset_out(gt_tx_pcs_reset),
.gt_tx_pma_reset_done_in(gt_tx_pma_reset_done),
@@ -432,6 +438,7 @@ gt_tx_reset_inst (
wire gt_rx_pd;
wire gt_rx_reset;
wire gt_rx_reset_done;
wire gt_userclk_rx_active;
wire gt_rx_pma_reset;
wire gt_rx_dfe_lpm_reset;
wire gt_rx_eyescan_reset;
@@ -448,7 +455,7 @@ taxi_sync_reset #(
.N(4)
)
rx_reset_sync_inst (
.clk(rx_clk),
.clk(rx_clk_in),
.rst(!rx_reset_done || rx_rst_in),
.out(rx_rst_out)
);
@@ -467,11 +474,11 @@ gt_rx_reset_inst (
/*
* GT
*/
.gt_rxusrclk2(rx_clk),
.gt_rxusrclk2(rx_clk_in),
.gt_rx_pd_out(gt_rx_pd),
.gt_rx_reset_out(gt_rx_reset),
.gt_rx_reset_done_in(gt_rx_reset_done),
.gt_userclk_rx_active_out(),
.gt_userclk_rx_active_out(gt_userclk_rx_active),
.gt_rx_pma_reset_out(gt_rx_pma_reset),
.gt_rx_dfe_lpm_reset_out(gt_rx_dfe_lpm_reset),
.gt_rx_eyescan_reset_out(gt_rx_eyescan_reset),
@@ -502,6 +509,35 @@ gt_rx_reset_inst (
.rx_lpm_en_in(ctrl_rxlpmen)
);
if (SIM) begin : clkbuf
assign tx_clk_out = gt_txoutclk;
assign rx_clk_out = gt_rxoutclk;
end else begin : clkbuf
BUFG_GT bufg_gt_txusrclk_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gt_tx_reset),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (gt_txoutclk),
.O (tx_clk_out)
);
BUFG_GT bufg_gt_rxusrclk_inst (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (gt_rx_reset),
.CLRMASK (1'b0),
.DIV (3'd0),
.I (gt_rxoutclk),
.O (rx_clk_out)
);
end
if (SIM) begin : xcvr
// simulation (no GT core)
@@ -577,16 +613,15 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && GT_USP) begin : xcvr
.gtyrxn_in(xcvr_rxn),
// Transmit
.gtwiz_userclk_tx_reset_in(gt_tx_reset),
.gtwiz_userclk_tx_srcclk_out(),
.gtwiz_userclk_tx_usrclk_out(),
.gtwiz_userclk_tx_usrclk2_out(tx_clk),
.gtwiz_userclk_tx_active_out(),
.gtwiz_userclk_tx_active_in(gt_userclk_tx_active),
.gtwiz_reset_tx_done_in(tx_reset_done),
.gtwiz_buffbypass_tx_reset_in(1'b0),
.gtwiz_buffbypass_tx_start_user_in(1'b0),
.gtwiz_buffbypass_tx_done_out(),
.gtwiz_buffbypass_tx_error_out(),
.txoutclk_out(gt_txoutclk),
.txusrclk_in(tx_clk_in),
.txusrclk2_in(tx_clk_in),
.txpdelecidlemode_in(1'b1),
.txpd_in(gt_tx_pd ? 2'b11 : 2'b00),
.gttxreset_in(gt_tx_reset),
@@ -613,16 +648,15 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && GT_USP) begin : xcvr
.txctrl1_in(serdes_txctrl1),
// Receive
.gtwiz_userclk_rx_reset_in(gt_rx_reset),
.gtwiz_userclk_rx_srcclk_out(),
.gtwiz_userclk_rx_usrclk_out(),
.gtwiz_userclk_rx_usrclk2_out(rx_clk),
.gtwiz_userclk_rx_active_out(),
.gtwiz_userclk_rx_active_in(gt_userclk_rx_active),
.gtwiz_reset_rx_done_in(rx_reset_done),
.gtwiz_buffbypass_rx_reset_in(1'b0),
.gtwiz_buffbypass_rx_start_user_in(1'b0),
.gtwiz_buffbypass_rx_done_out(),
.gtwiz_buffbypass_rx_error_out(),
.rxoutclk_out(gt_rxoutclk),
.rxusrclk_in(rx_clk_in),
.rxusrclk2_in(rx_clk_in),
.rxpd_in(gt_rx_pd ? 2'b11 : 2'b00),
.gtrxreset_in(gt_rx_reset),
.rxpmareset_in(gt_rx_pma_reset),
@@ -697,16 +731,15 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && !GT_USP) begin : xcvr
.gtyrxn_in(xcvr_rxn),
// Transmit
.gtwiz_userclk_tx_reset_in(gt_tx_reset),
.gtwiz_userclk_tx_srcclk_out(),
.gtwiz_userclk_tx_usrclk_out(),
.gtwiz_userclk_tx_usrclk2_out(tx_clk),
.gtwiz_userclk_tx_active_out(),
.gtwiz_userclk_tx_active_in(gt_userclk_tx_active),
.gtwiz_reset_tx_done_in(tx_reset_done),
.gtwiz_buffbypass_tx_reset_in(1'b0),
.gtwiz_buffbypass_tx_start_user_in(1'b0),
.gtwiz_buffbypass_tx_done_out(),
.gtwiz_buffbypass_tx_error_out(),
.txoutclk_out(gt_txoutclk),
.txusrclk_in(tx_clk_in),
.txusrclk2_in(tx_clk_in),
.txpdelecidlemode_in(1'b1),
.txpd_in(gt_tx_pd ? 2'b11 : 2'b00),
.gttxreset_in(gt_tx_reset),
@@ -733,16 +766,15 @@ end else if (HAS_COMMON && GT_TYPE == "GTY" && !GT_USP) begin : xcvr
.txctrl1_in(serdes_txctrl1),
// Receive
.gtwiz_userclk_rx_reset_in(gt_rx_reset),
.gtwiz_userclk_rx_srcclk_out(),
.gtwiz_userclk_rx_usrclk_out(),
.gtwiz_userclk_rx_usrclk2_out(rx_clk),
.gtwiz_userclk_rx_active_out(),
.gtwiz_userclk_rx_active_in(gt_userclk_rx_active),
.gtwiz_reset_rx_done_in(rx_reset_done),
.gtwiz_buffbypass_rx_reset_in(1'b0),
.gtwiz_buffbypass_rx_start_user_in(1'b0),
.gtwiz_buffbypass_rx_done_out(),
.gtwiz_buffbypass_rx_error_out(),
.rxoutclk_out(gt_rxoutclk),
.rxusrclk_in(rx_clk_in),
.rxusrclk2_in(rx_clk_in),
.rxpd_in(gt_rx_pd ? 2'b11 : 2'b00),
.gtrxreset_in(gt_rx_reset),
.rxpmareset_in(gt_rx_pma_reset),
@@ -800,16 +832,15 @@ end else if (!HAS_COMMON && GT_TYPE == "GTY") begin : xcvr
.gtyrxn_in(xcvr_rxn),
// Transmit
.gtwiz_userclk_tx_reset_in(gt_tx_reset),
.gtwiz_userclk_tx_srcclk_out(),
.gtwiz_userclk_tx_usrclk_out(),
.gtwiz_userclk_tx_usrclk2_out(tx_clk),
.gtwiz_userclk_tx_active_out(),
.gtwiz_userclk_tx_active_in(gt_userclk_tx_active),
.gtwiz_reset_tx_done_in(tx_reset_done),
.gtwiz_buffbypass_tx_reset_in(1'b0),
.gtwiz_buffbypass_tx_start_user_in(1'b0),
.gtwiz_buffbypass_tx_done_out(),
.gtwiz_buffbypass_tx_error_out(),
.txoutclk_out(gt_txoutclk),
.txusrclk_in(tx_clk_in),
.txusrclk2_in(tx_clk_in),
.txpdelecidlemode_in(1'b1),
.txpd_in(gt_tx_pd ? 2'b11 : 2'b00),
.gttxreset_in(gt_tx_reset),
@@ -836,16 +867,15 @@ end else if (!HAS_COMMON && GT_TYPE == "GTY") begin : xcvr
.txctrl1_in(serdes_txctrl1),
// Receive
.gtwiz_userclk_rx_reset_in(gt_rx_reset),
.gtwiz_userclk_rx_srcclk_out(),
.gtwiz_userclk_rx_usrclk_out(),
.gtwiz_userclk_rx_usrclk2_out(rx_clk),
.gtwiz_userclk_rx_active_out(),
.gtwiz_userclk_rx_active_in(gt_userclk_rx_active),
.gtwiz_reset_rx_done_in(rx_reset_done),
.gtwiz_buffbypass_rx_reset_in(1'b0),
.gtwiz_buffbypass_rx_start_user_in(1'b0),
.gtwiz_buffbypass_rx_done_out(),
.gtwiz_buffbypass_rx_error_out(),
.rxoutclk_out(gt_rxoutclk),
.rxusrclk_in(rx_clk_in),
.rxusrclk2_in(rx_clk_in),
.rxpd_in(gt_rx_pd ? 2'b11 : 2'b00),
.gtrxreset_in(gt_rx_reset),
.rxpmareset_in(gt_rx_pma_reset),

4
src/eth/rtl/us/taxi_eth_mac_100g_us_gty_156.tcl
View File

@@ -71,8 +71,8 @@ if {$sec_line_rate != 0} {
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {CORE}
dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
dict set config LOCATE_TX_USER_CLOCKING {CORE}
dict set config LOCATE_RX_USER_CLOCKING {CORE}
dict set config LOCATE_TX_USER_CLOCKING {EXAMPLE_DESIGN}
dict set config LOCATE_RX_USER_CLOCKING {EXAMPLE_DESIGN}
dict set config LOCATE_USER_DATA_WIDTH_SIZING {EXAMPLE_DESIGN}
dict set config FREERUN_FREQUENCY $freerun_freq
dict set config DISABLE_LOC_XDC {1}

4
src/eth/rtl/us/taxi_eth_mac_100g_us_gty_161.tcl
View File

@@ -71,8 +71,8 @@ if {$sec_line_rate != 0} {
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {CORE}
dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
dict set config LOCATE_TX_USER_CLOCKING {CORE}
dict set config LOCATE_RX_USER_CLOCKING {CORE}
dict set config LOCATE_TX_USER_CLOCKING {EXAMPLE_DESIGN}
dict set config LOCATE_RX_USER_CLOCKING {EXAMPLE_DESIGN}
dict set config LOCATE_USER_DATA_WIDTH_SIZING {EXAMPLE_DESIGN}
dict set config FREERUN_FREQUENCY $freerun_freq
dict set config DISABLE_LOC_XDC {1}

4
src/eth/rtl/us/taxi_eth_mac_100g_us_gty_322.tcl
View File

@@ -71,8 +71,8 @@ if {$sec_line_rate != 0} {
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
dict set config LOCATE_COMMON {CORE}
dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
dict set config LOCATE_TX_USER_CLOCKING {CORE}
dict set config LOCATE_RX_USER_CLOCKING {CORE}
dict set config LOCATE_TX_USER_CLOCKING {EXAMPLE_DESIGN}
dict set config LOCATE_RX_USER_CLOCKING {EXAMPLE_DESIGN}
dict set config LOCATE_USER_DATA_WIDTH_SIZING {EXAMPLE_DESIGN}
dict set config FREERUN_FREQUENCY $freerun_freq
dict set config DISABLE_LOC_XDC {1}