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example/Arty: Arty example design clean-up

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-04-09 19:12:57 -07:00
parent d355956b68
commit 28fd0f8cba
3 changed files with 4 additions and 5 deletions
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4
example/Arty/fpga/tb/fpga_core/test_fpga_core.py
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@@ -35,8 +35,8 @@ class TB:
self.mii_phy = MiiPhy(dut.phy_txd, None, dut.phy_tx_en, dut.phy_tx_clk,
dut.phy_rxd, dut.phy_rx_er, dut.phy_rx_dv, dut.phy_rx_clk, speed=speed)
self.uart_source = UartSource(dut.uart_rxd, baud=115200, bits=8, stop_bits=1)
self.uart_sink = UartSink(dut.uart_txd, baud=115200, bits=8, stop_bits=1)
self.uart_source = UartSource(dut.uart_rxd, baud=3000000, bits=8, stop_bits=1)
self.uart_sink = UartSink(dut.uart_txd, baud=3000000, bits=8, stop_bits=1)
dut.phy_crs.setimmediatevalue(0)
dut.phy_col.setimmediatevalue(0)