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cndm: Update KCU105 pins

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-03-13 19:47:00 -07:00
parent c280dd3da3
commit 29fadb6b16
4 changed files with 11 additions and 0 deletions
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6
src/cndm/board/KCU105/fpga/fpga.xdc
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@@ -45,6 +45,10 @@ create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p]
#set_property -dict {LOC C23 IOSTANDARD LVDS} [get_ports clk_user_sma_n] ;# J35 #set_property -dict {LOC C23 IOSTANDARD LVDS} [get_ports clk_user_sma_n] ;# J35
#create_clock -period 10.000 -name clk_user_sma [get_ports clk_user_sma_p] #create_clock -period 10.000 -name clk_user_sma [get_ports clk_user_sma_p]
# User SMA GPIO J36/J37
#set_property -dict {LOC H27 IOSTANDARD LVDS} [get_ports user_sma_gpio_p] ;# J36
#set_property -dict {LOC G27 IOSTANDARD LVDS} [get_ports user_sma_gpio_n] ;# J37
# LEDs # LEDs
set_property -dict {LOC AP8 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[0]}] ;# to DS7 set_property -dict {LOC AP8 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[0]}] ;# to DS7
set_property -dict {LOC H23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[1]}] ;# to DS6 set_property -dict {LOC H23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {led[1]}] ;# to DS6
@@ -172,7 +176,9 @@ set_property -dict {LOC P5 } [get_ports sfp_mgt_refclk_0_n] ;# MGTREFCLK0N_227
#set_property -dict {LOC AH11 IOSTANDARD LVDS} [get_ports sfp_recclk_n] ;# to U57 CKIN1 SI5328 #set_property -dict {LOC AH11 IOSTANDARD LVDS} [get_ports sfp_recclk_n] ;# to U57 CKIN1 SI5328
set_property -dict {LOC AL8 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {sfp_tx_disable_b[0]}] set_property -dict {LOC AL8 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {sfp_tx_disable_b[0]}]
set_property -dict {LOC K21 IOSTANDARD LVCMOS18} [get_ports {sfp_rx_los[0]}]
set_property -dict {LOC D28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {sfp_tx_disable_b[1]}] set_property -dict {LOC D28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {sfp_tx_disable_b[1]}]
set_property -dict {LOC AM9 IOSTANDARD LVCMOS18} [get_ports {sfp_rx_los[1]}]
# 156.25 MHz MGT reference clock # 156.25 MHz MGT reference clock
create_clock -period 6.400 -name sfp_mgt_refclk_0 [get_ports sfp_mgt_refclk_0_p] create_clock -period 6.400 -name sfp_mgt_refclk_0 [get_ports sfp_mgt_refclk_0_p]

2
src/cndm/board/KCU105/fpga/rtl/fpga.sv
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@@ -104,6 +104,7 @@ module fpga #
input wire logic sfp_mgt_refclk_0_n, input wire logic sfp_mgt_refclk_0_n,
output wire logic [1:0] sfp_tx_disable_b, output wire logic [1:0] sfp_tx_disable_b,
input wire logic [1:0] sfp_rx_los,
/* /*
* PCIe * PCIe
@@ -996,6 +997,7 @@ core_inst (
.sfp_mgt_refclk_0_n(sfp_mgt_refclk_0_n), .sfp_mgt_refclk_0_n(sfp_mgt_refclk_0_n),
.sfp_tx_disable_b(sfp_tx_disable_b), .sfp_tx_disable_b(sfp_tx_disable_b),
.sfp_rx_los(sfp_rx_los),
/* /*
* PCIe * PCIe

1
src/cndm/board/KCU105/fpga/rtl/fpga_core.sv
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@@ -110,6 +110,7 @@ module fpga_core #
input wire logic sfp_mgt_refclk_0_n, input wire logic sfp_mgt_refclk_0_n,
output wire logic [1:0] sfp_tx_disable_b, output wire logic [1:0] sfp_tx_disable_b,
input wire logic [1:0] sfp_rx_los,
/* /*
* PCIe * PCIe

2
src/cndm/board/KCU105/fpga/tb/fpga_core/test_fpga_core.sv
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@@ -94,6 +94,7 @@ logic sfp_mgt_refclk_0_p;
logic sfp_mgt_refclk_0_n; logic sfp_mgt_refclk_0_n;
logic [1:0] sfp_tx_disable_b; logic [1:0] sfp_tx_disable_b;
logic [1:0] sfp_rx_los;
logic pcie_clk; logic pcie_clk;
logic pcie_rst; logic pcie_rst;
@@ -281,6 +282,7 @@ uut (
.sfp_mgt_refclk_0_n(sfp_mgt_refclk_0_n), .sfp_mgt_refclk_0_n(sfp_mgt_refclk_0_n),
.sfp_tx_disable_b(sfp_tx_disable_b), .sfp_tx_disable_b(sfp_tx_disable_b),
.sfp_rx_los(sfp_rx_los),
/* /*
* PCIe * PCIe