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pcie: Remove TLP_HDR_W parameter from testbenches

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
2025-09-01 22:08:18 -07:00
parent cdfb1566f5
commit 2ae5b5fae3
6 changed files with 0 additions and 8 deletions
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src/pcie/tb/taxi_pcie_axil_master_minimal/Makefile
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@@ -35,7 +35,6 @@ VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_TLP_SEG_DATA_W := 64
export PARAM_TLP_HDR_W := 128
export PARAM_TLP_SEGS := 1
export PARAM_AXIL_DATA_W := 32
export PARAM_AXIL_ADDR_W := 64