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pcie: Remove TLP_HDR_W parameter from testbenches

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-09-01 22:08:18 -07:00
parent cdfb1566f5
commit 2ae5b5fae3
6 changed files with 0 additions and 8 deletions
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1
src/pcie/tb/taxi_pcie_axil_master/Makefile
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@@ -35,7 +35,6 @@ VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters # module parameters
export PARAM_TLP_SEG_DATA_W := 64 export PARAM_TLP_SEG_DATA_W := 64
export PARAM_TLP_HDR_W := 128
export PARAM_TLP_SEGS := 1 export PARAM_TLP_SEGS := 1
export PARAM_AXIL_DATA_W := 32 export PARAM_AXIL_DATA_W := 32
export PARAM_AXIL_ADDR_W := 64 export PARAM_AXIL_ADDR_W := 64

1
src/pcie/tb/taxi_pcie_axil_master/test_taxi_pcie_axil_master.py
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@@ -339,7 +339,6 @@ def test_taxi_pcie_axil_master(request, pcie_data_w, axil_data_w):
parameters = {} parameters = {}
parameters['TLP_SEG_DATA_W'] = pcie_data_w parameters['TLP_SEG_DATA_W'] = pcie_data_w
parameters['TLP_HDR_W'] = 128
parameters['TLP_SEGS'] = 1 parameters['TLP_SEGS'] = 1
parameters['AXIL_DATA_W'] = axil_data_w parameters['AXIL_DATA_W'] = axil_data_w
parameters['AXIL_ADDR_W'] = 64 parameters['AXIL_ADDR_W'] = 64

2
src/pcie/tb/taxi_pcie_axil_master/test_taxi_pcie_axil_master.sv
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@@ -19,7 +19,6 @@ module test_taxi_pcie_axil_master #
( (
/* verilator lint_off WIDTHTRUNC */ /* verilator lint_off WIDTHTRUNC */
parameter TLP_SEG_DATA_W = 64, parameter TLP_SEG_DATA_W = 64,
parameter TLP_HDR_W = 128,
parameter TLP_SEGS = 1, parameter TLP_SEGS = 1,
parameter AXIL_DATA_W = 32, parameter AXIL_DATA_W = 32,
parameter AXIL_ADDR_W = 64, parameter AXIL_ADDR_W = 64,
@@ -34,7 +33,6 @@ logic rst;
taxi_pcie_tlp_if #( taxi_pcie_tlp_if #(
.SEGS(TLP_SEGS), .SEGS(TLP_SEGS),
.SEG_DATA_W(TLP_SEG_DATA_W), .SEG_DATA_W(TLP_SEG_DATA_W),
.HDR_W(TLP_HDR_W),
.FUNC_NUM_W(8) .FUNC_NUM_W(8)
) rx_req_tlp(), tx_cpl_tlp(); ) rx_req_tlp(), tx_cpl_tlp();

1
src/pcie/tb/taxi_pcie_axil_master_minimal/Makefile
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@@ -35,7 +35,6 @@ VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters # module parameters
export PARAM_TLP_SEG_DATA_W := 64 export PARAM_TLP_SEG_DATA_W := 64
export PARAM_TLP_HDR_W := 128
export PARAM_TLP_SEGS := 1 export PARAM_TLP_SEGS := 1
export PARAM_AXIL_DATA_W := 32 export PARAM_AXIL_DATA_W := 32
export PARAM_AXIL_ADDR_W := 64 export PARAM_AXIL_ADDR_W := 64

1
src/pcie/tb/taxi_pcie_axil_master_minimal/test_taxi_pcie_axil_master_minimal.py
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@@ -374,7 +374,6 @@ def test_taxi_pcie_axil_master_minimal(request, pcie_data_w, axil_data_w):
parameters = {} parameters = {}
parameters['TLP_SEG_DATA_W'] = pcie_data_w parameters['TLP_SEG_DATA_W'] = pcie_data_w
parameters['TLP_HDR_W'] = 128
parameters['TLP_SEGS'] = 1 parameters['TLP_SEGS'] = 1
parameters['AXIL_DATA_W'] = axil_data_w parameters['AXIL_DATA_W'] = axil_data_w
parameters['AXIL_ADDR_W'] = 64 parameters['AXIL_ADDR_W'] = 64

2
src/pcie/tb/taxi_pcie_axil_master_minimal/test_taxi_pcie_axil_master_minimal.sv
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@@ -19,7 +19,6 @@ module test_taxi_pcie_axil_master_minimal #
( (
/* verilator lint_off WIDTHTRUNC */ /* verilator lint_off WIDTHTRUNC */
parameter TLP_SEG_DATA_W = 64, parameter TLP_SEG_DATA_W = 64,
parameter TLP_HDR_W = 128,
parameter TLP_SEGS = 1, parameter TLP_SEGS = 1,
parameter AXIL_DATA_W = 32, parameter AXIL_DATA_W = 32,
parameter AXIL_ADDR_W = 64, parameter AXIL_ADDR_W = 64,
@@ -34,7 +33,6 @@ logic rst;
taxi_pcie_tlp_if #( taxi_pcie_tlp_if #(
.SEGS(TLP_SEGS), .SEGS(TLP_SEGS),
.SEG_DATA_W(TLP_SEG_DATA_W), .SEG_DATA_W(TLP_SEG_DATA_W),
.HDR_W(TLP_HDR_W),
.FUNC_NUM_W(8) .FUNC_NUM_W(8)
) rx_req_tlp(), tx_cpl_tlp(); ) rx_req_tlp(), tx_cpl_tlp();