example/KCU105: Add example design for KCU105

Signed-off-by: Alex Forencich <alex@alexforencich.com>

example/KCU105/fpga/README.md

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+# Taxi Example Design for KCU105
+
+## Introduction
+
+This example design targets the Xilinx KCU105 FPGA board.
+
+The design places looped-back MACs on the BASE-T port and SFP+ cages, as well as a looped-back UART on on the USB UART connection.
+
+*  USB UART
+    *  Looped-back UART
+*  RJ-45 Ethernet port with Marvell 88E1111 PHY
+    *  Looped-back MAC via SGMII via Xilinx PCS/PMA core and LVDS IOSERDES
+*  SFP+ cages
+    *  Looped-back 1000BASE-X via Xilinx PCS/PMA core and GTH transceiver
+
+## Board details
+
+*  FPGA: xcku040-ffva1156-2-e
+*  1000BASE-T PHY: Marvell 88E1111 via SGMII
+
+## How to build
+
+Run `make` in the appropriate `fpga*` subdirectory to build the bitstream.  Ensure that the Xilinx Vivado toolchain components are in PATH.
+
+## How to test
+
+Run `make program` to program the board with Vivado.
+
+To test the looped-back UART, use any serial terminal software like minicom, screen, etc.  The looped-back UART will echo typed text back without modification.
+
+To test the looped-back MAC, it is recommended to use a network tester like the Viavi T-BERD 5800 that supports basic layer 2 tests with a loopback.  Do not connect the looped-back MAC to a network as the reflected packets may cause problems.