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cndm: Add support for VCU108
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
38
src/cndm/board/VCU108/fpga/README.md
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38
src/cndm/board/VCU108/fpga/README.md
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# Corundum for VCU108
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## Introduction
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This design targets the Xilinx VCU108 FPGA board.
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* USB UART
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* XFCP (921600 baud)
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* RJ-45 Ethernet port with Marvell 88E1111 PHY
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* Looped-back MAC via SGMII via Xilinx PCS/PMA core and LVDS IOSERDES
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* QSFP28
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* 10GBASE-R or 25GBASE-R MACs via GTY transceivers
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## Board details
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* FPGA: xcvu095-ffva2104-2-e
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* USB UART: Silicon Labs CP2105 SCI
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* PCIe: gen 3 x8 (~64 Gbps)
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* Reference oscillator: Fixed 156.25 MHz from Si570
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* 1000BASE-T PHY: Marvell 88E1111 via SGMII
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* 25GBASE-R PHY: Soft PCS with GTY transceivers
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## Licensing
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* Toolchain
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* Vivado Enterprise (requires license)
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* IP
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* No licensed vendor IP or 3rd party IP
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## How to build
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Run `make` in the appropriate `fpga*` subdirectory to build the bitstream. Ensure that the Xilinx Vivado toolchain components are in PATH.
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On the host system, run `make` in `modules/cndm` to build the driver. Ensure that the headers for the running kernel are installed, otherwise the driver cannot be compiled.
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## How to test
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Run `make program` to program the board with Vivado. Then, reboot the machine to re-enumerate the PCIe bus. Finally, load the driver on the host system with `insmod cndm.ko`. Check `dmesg` for output from driver initialization. Run `cndm_ddcmd.sh =p` to enable all debug messages.
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153
src/cndm/board/VCU108/fpga/common/vivado.mk
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153
src/cndm/board/VCU108/fpga/common/vivado.mk
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# SPDX-License-Identifier: MIT
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###################################################################
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#
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# Xilinx Vivado FPGA Makefile
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#
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# Copyright (c) 2016-2025 Alex Forencich
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#
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###################################################################
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#
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# Parameters:
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# FPGA_TOP - Top module name
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# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
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# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
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# SYN_FILES - list of source files
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# INC_FILES - list of include files
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# XDC_FILES - list of timing constraint files
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# XCI_FILES - list of IP XCI files
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# IP_TCL_FILES - list of IP TCL files (sourced during project creation)
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# CONFIG_TCL_FILES - list of config TCL files (sourced before each build)
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#
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# Note: both SYN_FILES and INC_FILES support file list files. File list
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# files are files with a .f extension that contain a list of additional
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# files to include, one path relative to the .f file location per line.
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# The .f files are processed recursively, and then the complete file list
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# is de-duplicated, with later files in the list taking precedence.
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#
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# Example:
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#
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# FPGA_TOP = fpga
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# FPGA_FAMILY = VirtexUltrascale
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# FPGA_DEVICE = xcvu095-ffva2104-2-e
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# SYN_FILES = rtl/fpga.v
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# XDC_FILES = fpga.xdc
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# XCI_FILES = ip/pcspma.xci
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# include ../common/vivado.mk
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#
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###################################################################
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# phony targets
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.PHONY: fpga vivado tmpclean clean distclean
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# prevent make from deleting intermediate files and reports
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.PRECIOUS: %.xpr %.bit %.bin %.ltx %.xsa %.mcs %.prm
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.SECONDARY:
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CONFIG ?= config.mk
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-include $(CONFIG)
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FPGA_TOP ?= fpga
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PROJECT ?= $(FPGA_TOP)
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XDC_FILES ?= $(PROJECT).xdc
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# handle file list files
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process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
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process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
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uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
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SYN_FILES := $(call uniq_base,$(call process_f_files,$(SYN_FILES)))
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INC_FILES := $(call uniq_base,$(call process_f_files,$(INC_FILES)))
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###################################################################
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# Main Targets
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#
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# all: build everything (fpga)
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# fpga: build FPGA config
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# vivado: open project in Vivado
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# tmpclean: remove intermediate files
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# clean: remove output files and project files
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# distclean: remove archived output files
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###################################################################
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all: fpga
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fpga: $(PROJECT).bit
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vivado: $(PROJECT).xpr
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vivado $(PROJECT).xpr
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tmpclean::
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-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
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-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
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clean:: tmpclean
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-rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
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-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
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distclean:: clean
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-rm -rf rev
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###################################################################
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# Target implementations
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###################################################################
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# Vivado project file
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# create fresh project if Makefile or IP files have changed
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create_project.tcl: Makefile $(XCI_FILES) $(IP_TCL_FILES)
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rm -rf defines.v
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touch defines.v
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for x in $(DEFS); do echo '`define' $$x >> defines.v; done
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echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
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echo "add_files -fileset sources_1 defines.v $(SYN_FILES)" >> $@
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echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
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echo "add_files -fileset constrs_1 $(XDC_FILES)" >> $@
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for x in $(XCI_FILES); do echo "import_ip $$x" >> $@; done
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for x in $(IP_TCL_FILES); do echo "source $$x" >> $@; done
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for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
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# source config TCL scripts if any source file has changed
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update_config.tcl: $(CONFIG_TCL_FILES) $(SYN_FILES) $(INC_FILES) $(XDC_FILES)
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echo "open_project -quiet $(PROJECT).xpr" > $@
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for x in $(CONFIG_TCL_FILES); do echo "source $$x" >> $@; done
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$(PROJECT).xpr: create_project.tcl update_config.tcl
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vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
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# synthesis run
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$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES) $(INC_FILES) $(XDC_FILES) | $(PROJECT).xpr
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echo "open_project $(PROJECT).xpr" > run_synth.tcl
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echo "reset_run synth_1" >> run_synth.tcl
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echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
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echo "wait_on_run synth_1" >> run_synth.tcl
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vivado -nojournal -nolog -mode batch -source run_synth.tcl
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# implementation run
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$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
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echo "open_project $(PROJECT).xpr" > run_impl.tcl
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echo "reset_run impl_1" >> run_impl.tcl
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echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
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echo "wait_on_run impl_1" >> run_impl.tcl
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echo "open_run impl_1" >> run_impl.tcl
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echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
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echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
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vivado -nojournal -nolog -mode batch -source run_impl.tcl
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# output files (including potentially bit, bin, ltx, and xsa)
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$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
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echo "open_project $(PROJECT).xpr" > generate_bit.tcl
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echo "open_run impl_1" >> generate_bit.tcl
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echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
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echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
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echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl
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vivado -nojournal -nolog -mode batch -source generate_bit.tcl
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ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
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ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin .
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if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
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mkdir -p rev
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COUNT=100; \
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while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
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do COUNT=$$((COUNT+1)); done; \
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cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
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cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \
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if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \
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if [ -e $(PROJECT).xsa ]; then cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa; fi
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984
src/cndm/board/VCU108/fpga/fpga.xdc
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984
src/cndm/board/VCU108/fpga/fpga.xdc
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# SPDX-License-Identifier: MIT
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#
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# Copyright (c) 2014-2025 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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#
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# XDC constraints for the Xilinx VCU108 board
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# part: xcvu095-ffva2104-2-e
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# General configuration
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set_property CFGBVS GND [current_design]
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set_property CONFIG_VOLTAGE 1.8 [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
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set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
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set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type1 [current_design]
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set_property CONFIG_MODE BPI16 [current_design]
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set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
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# System clocks
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# 300 MHz
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#set_property -dict {LOC G31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_p]
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#set_property -dict {LOC F31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_n]
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#create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p]
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#set_property -dict {LOC G22 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_2_p]
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#set_property -dict {LOC G21 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_2_n]
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#create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p]
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# 125 MHz
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set_property -dict {LOC BC9 IOSTANDARD LVDS} [get_ports clk_125mhz_p]
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set_property -dict {LOC BC8 IOSTANDARD LVDS} [get_ports clk_125mhz_n]
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create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p]
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# 90 MHz
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#set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz]
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#create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz]
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# User SMA clock J34/J35
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#set_property -dict {LOC AR14 IOSTANDARD LVDS} [get_ports user_sma_clk_p]
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#set_property -dict {LOC AT14 IOSTANDARD LVDS} [get_ports user_sma_clk_n]
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#create_clock -period 8.000 -name user_sma_clk [get_ports user_sma_clk_p]
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# LEDs
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set_property -dict {LOC AT32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}] ;# DS7
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set_property -dict {LOC AV34 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}] ;# DS6
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set_property -dict {LOC AY30 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[2]}] ;# DS8
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set_property -dict {LOC BB32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[3]}] ;# DS9
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set_property -dict {LOC BF32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[4]}] ;# DS10
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set_property -dict {LOC AV36 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[5]}] ;# DS33
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set_property -dict {LOC AY35 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[6]}] ;# DS32
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set_property -dict {LOC BA37 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[7]}] ;# DS31
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set_false_path -to [get_ports {led[*]}]
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set_output_delay 0 [get_ports {led[*]}]
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# Reset button
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set_property -dict {LOC E36 IOSTANDARD LVCMOS12} [get_ports reset] ;# SW5
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set_false_path -from [get_ports {reset}]
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set_input_delay 0 [get_ports {reset}]
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# Push buttons
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set_property -dict {LOC E34 IOSTANDARD LVCMOS12} [get_ports btnu] ;# SW10
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set_property -dict {LOC M22 IOSTANDARD LVCMOS12} [get_ports btnl] ;# SW6
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set_property -dict {LOC D9 IOSTANDARD LVCMOS12} [get_ports btnd] ;# SW17
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set_property -dict {LOC A10 IOSTANDARD LVCMOS12} [get_ports btnr] ;# SW9
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set_property -dict {LOC AW27 IOSTANDARD LVCMOS12} [get_ports btnc] ;# SW7
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set_false_path -from [get_ports {btnu btnl btnd btnr btnc}]
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set_input_delay 0 [get_ports {btnu btnl btnd btnr btnc}]
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# DIP switches
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set_property -dict {LOC BC40 IOSTANDARD LVCMOS12} [get_ports {sw[0]}] ;# SW12.4
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set_property -dict {LOC L19 IOSTANDARD LVCMOS12} [get_ports {sw[1]}] ;# SW12.3
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set_property -dict {LOC C37 IOSTANDARD LVCMOS12} [get_ports {sw[2]}] ;# SW12.2
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set_property -dict {LOC C38 IOSTANDARD LVCMOS12} [get_ports {sw[3]}] ;# SW12.1
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set_false_path -from [get_ports {sw[*]}]
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set_input_delay 0 [get_ports {sw[*]}]
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# PMOD0
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#set_property -dict {LOC BC14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[0]}] ;# J52.1
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#set_property -dict {LOC BA10 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[1]}] ;# J52.3
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#set_property -dict {LOC AW16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[2]}] ;# J52.5
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||||||
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#set_property -dict {LOC BB16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[3]}] ;# J52.7
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||||||
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#set_property -dict {LOC BC13 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[4]}] ;# J52.2
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||||||
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#set_property -dict {LOC BF7 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[5]}] ;# J52.4
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||||||
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#set_property -dict {LOC AW12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[6]}] ;# J52.6
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||||||
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#set_property -dict {LOC BC16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[7]}] ;# J52.8
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||||||
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||||||
|
#set_false_path -to [get_ports {pmod0[*]}]
|
||||||
|
#set_output_delay 0 [get_ports {pmod0[*]}]
|
||||||
|
|
||||||
|
# PMOD1
|
||||||
|
#set_property -dict {LOC P22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[0]}] ;# J53.1
|
||||||
|
#set_property -dict {LOC N22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[1]}] ;# J53.3
|
||||||
|
#set_property -dict {LOC J20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[2]}] ;# J53.5
|
||||||
|
#set_property -dict {LOC K24 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[3]}] ;# J53.7
|
||||||
|
#set_property -dict {LOC J24 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[4]}] ;# J53.2
|
||||||
|
#set_property -dict {LOC T23 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[5]}] ;# J53.4
|
||||||
|
#set_property -dict {LOC R23 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[6]}] ;# J53.6
|
||||||
|
#set_property -dict {LOC R22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[7]}] ;# J53.8
|
||||||
|
|
||||||
|
#set_false_path -to [get_ports {pmod1[*]}]
|
||||||
|
#set_output_delay 0 [get_ports {pmod1[*]}]
|
||||||
|
|
||||||
|
# UART (U34 CP2105 SCI)
|
||||||
|
set_property -dict {LOC BE24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd}] ;# U34.20 RXD_SCI_I
|
||||||
|
set_property -dict {LOC BC24 IOSTANDARD LVCMOS18} [get_ports {uart_rxd}] ;# U34.21 TXD_SCI_O
|
||||||
|
set_property -dict {LOC BF24 IOSTANDARD LVCMOS18} [get_ports {uart_rts}] ;# U34.19 RTS_SCI_O
|
||||||
|
set_property -dict {LOC BD22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_cts}] ;# U34.18 CTS_SCI_I
|
||||||
|
|
||||||
|
set_false_path -to [get_ports {uart_txd uart_cts}]
|
||||||
|
set_output_delay 0 [get_ports {uart_txd uart_cts}]
|
||||||
|
set_false_path -from [get_ports {uart_rxd uart_rts}]
|
||||||
|
set_input_delay 0 [get_ports {uart_rxd uart_rts}]
|
||||||
|
|
||||||
|
# I2C interface
|
||||||
|
#set_property -dict {LOC AN21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_scl]
|
||||||
|
#set_property -dict {LOC AP21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_sda]
|
||||||
|
|
||||||
|
#set_false_path -to [get_ports {i2c_sda i2c_scl}]
|
||||||
|
#set_output_delay 0 [get_ports {i2c_sda i2c_scl}]
|
||||||
|
#set_false_path -from [get_ports {i2c_sda i2c_scl}]
|
||||||
|
#set_input_delay 0 [get_ports {i2c_sda i2c_scl}]
|
||||||
|
|
||||||
|
# Gigabit Ethernet SGMII PHY
|
||||||
|
set_property -dict {LOC AR24 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_sgmii_rx_p]
|
||||||
|
set_property -dict {LOC AT24 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_sgmii_rx_n]
|
||||||
|
set_property -dict {LOC AR23 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_sgmii_tx_p]
|
||||||
|
set_property -dict {LOC AR22 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_sgmii_tx_n]
|
||||||
|
set_property -dict {LOC AT22 IOSTANDARD LVDS_25} [get_ports phy_sgmii_clk_p]
|
||||||
|
set_property -dict {LOC AU22 IOSTANDARD LVDS_25} [get_ports phy_sgmii_clk_n]
|
||||||
|
set_property -dict {LOC AU21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_reset_n]
|
||||||
|
set_property -dict {LOC AT21 IOSTANDARD LVCMOS18} [get_ports phy_int_n]
|
||||||
|
#set_property -dict {LOC AV24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_mdio]
|
||||||
|
#set_property -dict {LOC AV21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_mdc]
|
||||||
|
|
||||||
|
# 625 MHz ref clock from SGMII PHY
|
||||||
|
#create_clock -period 1.600 -name phy_sgmii_clk [get_ports phy_sgmii_clk_p]
|
||||||
|
|
||||||
|
set_false_path -to [get_ports {phy_reset_n}]
|
||||||
|
set_output_delay 0 [get_ports {phy_reset_n}]
|
||||||
|
set_false_path -from [get_ports {phy_int_n}]
|
||||||
|
set_input_delay 0 [get_ports {phy_int_n}]
|
||||||
|
|
||||||
|
#set_false_path -to [get_ports {phy_mdio phy_mdc}]
|
||||||
|
#set_output_delay 0 [get_ports {phy_mdio phy_mdc}]
|
||||||
|
#set_false_path -from [get_ports {phy_mdio}]
|
||||||
|
#set_input_delay 0 [get_ports {phy_mdio}]
|
||||||
|
|
||||||
|
# Bullseye GTY
|
||||||
|
#set_property -dict {LOC AR45} [get_ports {bullseye_rx_p[0]}] ;# MGTYRXP0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2
|
||||||
|
#set_property -dict {LOC AR46} [get_ports {bullseye_rx_n[0]}] ;# MGTYRXN0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2
|
||||||
|
#set_property -dict {LOC AT42} [get_ports {bullseye_tx_p[0]}] ;# MGTYTXP0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2
|
||||||
|
#set_property -dict {LOC AT43} [get_ports {bullseye_tx_n[0]}] ;# MGTYTXN0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2
|
||||||
|
#set_property -dict {LOC AN45} [get_ports {bullseye_rx_p[1]}] ;# MGTYRXP1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2
|
||||||
|
#set_property -dict {LOC AN46} [get_ports {bullseye_rx_n[1]}] ;# MGTYRXN1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2
|
||||||
|
#set_property -dict {LOC AP42} [get_ports {bullseye_tx_p[1]}] ;# MGTYTXP1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2
|
||||||
|
#set_property -dict {LOC AP43} [get_ports {bullseye_tx_n[1]}] ;# MGTYTXN1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2
|
||||||
|
#set_property -dict {LOC AL45} [get_ports {bullseye_rx_p[2]}] ;# MGTYRXP2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2
|
||||||
|
#set_property -dict {LOC AL46} [get_ports {bullseye_rx_n[2]}] ;# MGTYRXN2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2
|
||||||
|
#set_property -dict {LOC AM42} [get_ports {bullseye_tx_p[2]}] ;# MGTYTXP2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2
|
||||||
|
#set_property -dict {LOC AM43} [get_ports {bullseye_tx_n[2]}] ;# MGTYTXN2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2
|
||||||
|
#set_property -dict {LOC AJ45} [get_ports {bullseye_rx_p[3]}] ;# MGTYRXP3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2
|
||||||
|
#set_property -dict {LOC AJ46} [get_ports {bullseye_rx_n[3]}] ;# MGTYRXN3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2
|
||||||
|
#set_property -dict {LOC AL40} [get_ports {bullseye_tx_p[3]}] ;# MGTYTXP3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2
|
||||||
|
#set_property -dict {LOC AL41} [get_ports {bullseye_tx_n[3]}] ;# MGTYTXN3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2
|
||||||
|
#set_property -dict {LOC AK38} [get_ports bullseye_mgt_refclk_0_p] ;# MGTREFCLK0P_126 from J87 P19
|
||||||
|
#set_property -dict {LOC AK39} [get_ports bullseye_mgt_refclk_0_n] ;# MGTREFCLK0N_126 from J87 P20
|
||||||
|
#set_property -dict {LOC AH38} [get_ports bullseye_mgt_refclk_1_p] ;# MGTREFCLK1P_126 from U32 SI570 via U104 SI53340
|
||||||
|
#set_property -dict {LOC AH39} [get_ports bullseye_mgt_refclk_1_n] ;# MGTREFCLK1N_126 from U32 SI570 via U104 SI53340
|
||||||
|
|
||||||
|
# 156.25 MHz MGT reference clock
|
||||||
|
#create_clock -period 6.4 -name bullseye_mgt_refclk [get_ports bullseye_mgt_refclk_1_p]
|
||||||
|
|
||||||
|
# QSFP28 Interface
|
||||||
|
set_property -dict {LOC AG45} [get_ports {qsfp_rx_p[0]}] ;# MGTYRXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
|
||||||
|
set_property -dict {LOC AG46} [get_ports {qsfp_rx_n[0]}] ;# MGTYRXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
|
||||||
|
set_property -dict {LOC AK42} [get_ports {qsfp_tx_p[0]}] ;# MGTYTXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
|
||||||
|
set_property -dict {LOC AK43} [get_ports {qsfp_tx_n[0]}] ;# MGTYTXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
|
||||||
|
set_property -dict {LOC AF43} [get_ports {qsfp_rx_p[1]}] ;# MGTYRXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
|
||||||
|
set_property -dict {LOC AF44} [get_ports {qsfp_rx_n[1]}] ;# MGTYRXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
|
||||||
|
set_property -dict {LOC AJ40} [get_ports {qsfp_tx_p[1]}] ;# MGTYTXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
|
||||||
|
set_property -dict {LOC AJ41} [get_ports {qsfp_tx_n[1]}] ;# MGTYTXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
|
||||||
|
set_property -dict {LOC AE45} [get_ports {qsfp_rx_p[2]}] ;# MGTYRXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
|
||||||
|
set_property -dict {LOC AE46} [get_ports {qsfp_rx_n[2]}] ;# MGTYRXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
|
||||||
|
set_property -dict {LOC AG40} [get_ports {qsfp_tx_p[2]}] ;# MGTYTXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
|
||||||
|
set_property -dict {LOC AG41} [get_ports {qsfp_tx_n[2]}] ;# MGTYTXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
|
||||||
|
set_property -dict {LOC AD43} [get_ports {qsfp_rx_p[3]}] ;# MGTYRXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
|
||||||
|
set_property -dict {LOC AD44} [get_ports {qsfp_rx_n[3]}] ;# MGTYRXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
|
||||||
|
set_property -dict {LOC AE40} [get_ports {qsfp_tx_p[3]}] ;# MGTYTXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
|
||||||
|
set_property -dict {LOC AE41} [get_ports {qsfp_tx_n[3]}] ;# MGTYTXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
|
||||||
|
set_property -dict {LOC AF38} [get_ports qsfp_mgt_refclk_0_p] ;# MGTREFCLK0P_127 from U32 SI570 via U102 SI53340
|
||||||
|
set_property -dict {LOC AF39} [get_ports qsfp_mgt_refclk_0_n] ;# MGTREFCLK0N_127 from U32 SI570 via U102 SI53340
|
||||||
|
#set_property -dict {LOC AD38} [get_ports qsfp_mgt_refclk_1_p] ;# MGTREFCLK1P_127 from U57 CKOUT2 SI5328
|
||||||
|
#set_property -dict {LOC AD39} [get_ports qsfp_mgt_refclk_1_n] ;# MGTREFCLK1N_127 from U57 CKOUT2 SI5328
|
||||||
|
#set_property -dict {LOC AG34 IOSTANDARD LVDS} [get_ports qsfp_recclk_p] ;# to U57 CKIN1 SI5328
|
||||||
|
#set_property -dict {LOC AH35 IOSTANDARD LVDS} [get_ports qsfp_recclk_n] ;# to U57 CKIN1 SI5328
|
||||||
|
set_property -dict {LOC AL24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_modsell]
|
||||||
|
set_property -dict {LOC AM24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_resetl]
|
||||||
|
set_property -dict {LOC AL25 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_modprsl]
|
||||||
|
set_property -dict {LOC AL21 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_intl]
|
||||||
|
set_property -dict {LOC AM21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_lpmode]
|
||||||
|
|
||||||
|
# 156.25 MHz MGT reference clock
|
||||||
|
create_clock -period 6.400 -name qsfp_mgt_refclk_0 [get_ports qsfp_mgt_refclk_0_p]
|
||||||
|
|
||||||
|
set_false_path -to [get_ports {qsfp_modsell qsfp_resetl qsfp_lpmode}]
|
||||||
|
set_output_delay 0 [get_ports {qsfp_modsell qsfp_resetl qsfp_lpmode}]
|
||||||
|
set_false_path -from [get_ports {qsfp_modprsl qsfp_intl}]
|
||||||
|
set_input_delay 0 [get_ports {qsfp_modprsl qsfp_intl}]
|
||||||
|
|
||||||
|
# CFP2 GTY
|
||||||
|
#set_property -dict {LOC J45 } [get_ports {cfp2_rx_p[0]}] ;# MGTYRXP1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
|
||||||
|
#set_property -dict {LOC J46 } [get_ports {cfp2_rx_n[0]}] ;# MGTYRXN1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
|
||||||
|
#set_property -dict {LOC F42 } [get_ports {cfp2_tx_p[0]}] ;# MGTYTXP1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
|
||||||
|
#set_property -dict {LOC F43 } [get_ports {cfp2_tx_n[0]}] ;# MGTYTXN1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
|
||||||
|
#set_property -dict {LOC N45 } [get_ports {cfp2_rx_p[1]}] ;# MGTYRXP3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
|
||||||
|
#set_property -dict {LOC N46 } [get_ports {cfp2_rx_n[1]}] ;# MGTYRXN3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
|
||||||
|
#set_property -dict {LOC K42 } [get_ports {cfp2_tx_p[1]}] ;# MGTYTXP3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
|
||||||
|
#set_property -dict {LOC K43 } [get_ports {cfp2_tx_n[1]}] ;# MGTYTXN3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
|
||||||
|
#set_property -dict {LOC R45 } [get_ports {cfp2_rx_p[2]}] ;# MGTYRXP2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
|
||||||
|
#set_property -dict {LOC R46 } [get_ports {cfp2_rx_n[2]}] ;# MGTYRXN2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
|
||||||
|
#set_property -dict {LOC M42 } [get_ports {cfp2_tx_p[2]}] ;# MGTYTXP2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
|
||||||
|
#set_property -dict {LOC M43 } [get_ports {cfp2_tx_n[2]}] ;# MGTYTXN2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
|
||||||
|
#set_property -dict {LOC L45 } [get_ports {cfp2_rx_p[3]}] ;# MGTYRXP0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
|
||||||
|
#set_property -dict {LOC L46 } [get_ports {cfp2_rx_n[3]}] ;# MGTYRXN0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
|
||||||
|
#set_property -dict {LOC H42 } [get_ports {cfp2_tx_p[3]}] ;# MGTYTXP0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
|
||||||
|
#set_property -dict {LOC H43 } [get_ports {cfp2_tx_n[3]}] ;# MGTYTXN0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
|
||||||
|
#set_property -dict {LOC Y43 } [get_ports {cfp2_rx_p[4]}] ;# MGTYRXP3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC Y44 } [get_ports {cfp2_rx_n[4]}] ;# MGTYRXN3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC U40 } [get_ports {cfp2_tx_p[4]}] ;# MGTYTXP3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC U41 } [get_ports {cfp2_tx_n[4]}] ;# MGTYTXN3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC U45 } [get_ports {cfp2_rx_p[5]}] ;# MGTYRXP1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
|
||||||
|
#set_property -dict {LOC U46 } [get_ports {cfp2_rx_n[5]}] ;# MGTYRXN1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
|
||||||
|
#set_property -dict {LOC P42 } [get_ports {cfp2_tx_p[5]}] ;# MGTYTXP1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
|
||||||
|
#set_property -dict {LOC P43 } [get_ports {cfp2_tx_n[5]}] ;# MGTYTXN1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
|
||||||
|
#set_property -dict {LOC W45 } [get_ports {cfp2_rx_p[6]}] ;# MGTYRXP0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
|
||||||
|
#set_property -dict {LOC W46 } [get_ports {cfp2_rx_n[6]}] ;# MGTYRXN0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
|
||||||
|
#set_property -dict {LOC T42 } [get_ports {cfp2_tx_p[6]}] ;# MGTYTXP0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
|
||||||
|
#set_property -dict {LOC T43 } [get_ports {cfp2_tx_n[6]}] ;# MGTYTXN0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
|
||||||
|
#set_property -dict {LOC AA45} [get_ports {cfp2_rx_p[7]}] ;# MGTYRXP2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC AA46} [get_ports {cfp2_rx_n[7]}] ;# MGTYRXN2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC W40 } [get_ports {cfp2_tx_p[7]}] ;# MGTYTXP2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC W41 } [get_ports {cfp2_tx_n[7]}] ;# MGTYTXN2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC AB43} [get_ports {cfp2_rx_p[8]}] ;# MGTYRXP1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC AB44} [get_ports {cfp2_rx_n[8]}] ;# MGTYRXN1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC AA40} [get_ports {cfp2_tx_p[8]}] ;# MGTYTXP1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC AA41} [get_ports {cfp2_tx_n[8]}] ;# MGTYTXN1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC AC45} [get_ports {cfp2_rx_p[9]}] ;# MGTYRXP0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC AC46} [get_ports {cfp2_rx_n[9]}] ;# MGTYRXN0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC AC40} [get_ports {cfp2_tx_p[9]}] ;# MGTYTXP0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC AC41} [get_ports {cfp2_tx_n[9]}] ;# MGTYTXN0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4
|
||||||
|
#set_property -dict {LOC V38 } [get_ports cfp2_mgt_refclk_0_p] ;# MGTREFCLK0P_129 from U32 SI570 via U104 SI53340
|
||||||
|
#set_property -dict {LOC V39 } [get_ports cfp2_mgt_refclk_0_n] ;# MGTREFCLK0N_129 from U32 SI570 via U104 SI53340
|
||||||
|
#set_property -dict {LOC T38 } [get_ports cfp2_mgt_refclk_1_p] ;# MGTREFCLK1P_129 from U57 CKOUT1 SI5328
|
||||||
|
#set_property -dict {LOC T39 } [get_ports cfp2_mgt_refclk_1_n] ;# MGTREFCLK1N_129 from U57 CKOUT1 SI5328
|
||||||
|
#set_property -dict {LOC BA21 IOSTANDARD LVCMOS18} [get_ports {cfp2_prg_cntl[0]}]
|
||||||
|
#set_property -dict {LOC AY24 IOSTANDARD LVCMOS18} [get_ports {cfp2_prg_cntl[1]}]
|
||||||
|
#set_property -dict {LOC AY23 IOSTANDARD LVCMOS18} [get_ports {cfp2_prg_cntl[2]}]
|
||||||
|
#set_property -dict {LOC BB24 IOSTANDARD LVCMOS18} [get_ports {cfp2_prg_alrm[0]}]
|
||||||
|
#set_property -dict {LOC BB23 IOSTANDARD LVCMOS18} [get_ports {cfp2_prg_alrm[1]}]
|
||||||
|
#set_property -dict {LOC BB22 IOSTANDARD LVCMOS18} [get_ports {cfp2_prg_alrm[2]}]
|
||||||
|
#set_property -dict {LOC BA22 IOSTANDARD LVCMOS18} [get_ports {cfp2_prtadr[0]}]
|
||||||
|
#set_property -dict {LOC AW25 IOSTANDARD LVCMOS18} [get_ports {cfp2_prtadr[1]}]
|
||||||
|
#set_property -dict {LOC AY25 IOSTANDARD LVCMOS18} [get_ports {cfp2_prtadr[2]}]
|
||||||
|
#set_property -dict {LOC AY22 IOSTANDARD LVCMOS18} [get_ports cfp2_tx_dis]
|
||||||
|
#set_property -dict {LOC BB21 IOSTANDARD LVCMOS18} [get_ports cfp2_rx_los]
|
||||||
|
#set_property -dict {LOC BC21 IOSTANDARD LVCMOS18} [get_ports cfp2_mod_lopwr]
|
||||||
|
#set_property -dict {LOC BD21 IOSTANDARD LVCMOS18} [get_ports cfp2_mod_rstn]
|
||||||
|
#set_property -dict {LOC BA25 IOSTANDARD LVCMOS18} [get_ports cfp2_mod_abs]
|
||||||
|
#set_property -dict {LOC BA24 IOSTANDARD LVCMOS18} [get_ports cfp2_glb_alrmn]
|
||||||
|
#set_property -dict {LOC BE22 IOSTANDARD LVCMOS18} [get_ports cfp2_mdc]
|
||||||
|
#set_property -dict {LOC BF22 IOSTANDARD LVCMOS18} [get_ports cfp2_mdio]
|
||||||
|
|
||||||
|
# 156.25 MHz MGT reference clock
|
||||||
|
#create_clock -period 6.4 -name cfp2_mgt_refclk [get_ports cfp2_mgt_refclk_0_p]
|
||||||
|
|
||||||
|
# PCIe Interface
|
||||||
|
set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[0]}] ;# MGTHRXP3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
|
||||||
|
set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[0]}] ;# MGTHRXN3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
|
||||||
|
set_property -dict {LOC AP7 } [get_ports {pcie_tx_p[0]}] ;# MGTHTXP3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
|
||||||
|
set_property -dict {LOC AP6 } [get_ports {pcie_tx_n[0]}] ;# MGTHTXN3_225 GTHE3_CHANNEL_X0Y7 / GTHE3_COMMON_X0Y1
|
||||||
|
set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[1]}] ;# MGTHRXP2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
|
||||||
|
set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[1]}] ;# MGTHRXN2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
|
||||||
|
set_property -dict {LOC AR5 } [get_ports {pcie_tx_p[1]}] ;# MGTHTXP2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
|
||||||
|
set_property -dict {LOC AR4 } [get_ports {pcie_tx_n[1]}] ;# MGTHTXN2_225 GTHE3_CHANNEL_X0Y6 / GTHE3_COMMON_X0Y1
|
||||||
|
set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[2]}] ;# MGTHRXP1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
|
||||||
|
set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[2]}] ;# MGTHRXN1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
|
||||||
|
set_property -dict {LOC AT7 } [get_ports {pcie_tx_p[2]}] ;# MGTHTXP1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
|
||||||
|
set_property -dict {LOC AT6 } [get_ports {pcie_tx_n[2]}] ;# MGTHTXN1_225 GTHE3_CHANNEL_X0Y5 / GTHE3_COMMON_X0Y1
|
||||||
|
set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[3]}] ;# MGTHRXP0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
|
||||||
|
set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[3]}] ;# MGTHRXN0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
|
||||||
|
set_property -dict {LOC AU5 } [get_ports {pcie_tx_p[3]}] ;# MGTHTXP0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
|
||||||
|
set_property -dict {LOC AU4 } [get_ports {pcie_tx_n[3]}] ;# MGTHTXN0_225 GTHE3_CHANNEL_X0Y4 / GTHE3_COMMON_X0Y1
|
||||||
|
set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[4]}] ;# MGTHRXP3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
|
||||||
|
set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[4]}] ;# MGTHRXN3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
|
||||||
|
set_property -dict {LOC AW5 } [get_ports {pcie_tx_p[4]}] ;# MGTHTXP3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
|
||||||
|
set_property -dict {LOC AW4 } [get_ports {pcie_tx_n[4]}] ;# MGTHTXN3_224 GTHE3_CHANNEL_X0Y3 / GTHE3_COMMON_X0Y0
|
||||||
|
set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[5]}] ;# MGTHRXP2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
|
||||||
|
set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[5]}] ;# MGTHRXN2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
|
||||||
|
set_property -dict {LOC BA5 } [get_ports {pcie_tx_p[5]}] ;# MGTHTXP2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
|
||||||
|
set_property -dict {LOC BA4 } [get_ports {pcie_tx_n[5]}] ;# MGTHTXN2_224 GTHE3_CHANNEL_X0Y2 / GTHE3_COMMON_X0Y0
|
||||||
|
set_property -dict {LOC AY2 } [get_ports {pcie_rx_p[6]}] ;# MGTHRXP1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
|
||||||
|
set_property -dict {LOC AY1 } [get_ports {pcie_rx_n[6]}] ;# MGTHRXN1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
|
||||||
|
set_property -dict {LOC BC5 } [get_ports {pcie_tx_p[6]}] ;# MGTHTXP1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
|
||||||
|
set_property -dict {LOC BC4 } [get_ports {pcie_tx_n[6]}] ;# MGTHTXN1_224 GTHE3_CHANNEL_X0Y1 / GTHE3_COMMON_X0Y0
|
||||||
|
set_property -dict {LOC BB2 } [get_ports {pcie_rx_p[7]}] ;# MGTHRXP0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
|
||||||
|
set_property -dict {LOC BB1 } [get_ports {pcie_rx_n[7]}] ;# MGTHRXN0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
|
||||||
|
set_property -dict {LOC BE5 } [get_ports {pcie_tx_p[7]}] ;# MGTHTXP0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
|
||||||
|
set_property -dict {LOC BE4 } [get_ports {pcie_tx_n[7]}] ;# MGTHTXN0_224 GTHE3_CHANNEL_X0Y0 / GTHE3_COMMON_X0Y0
|
||||||
|
set_property -dict {LOC AL9 } [get_ports pcie_refclk_p] ;# MGTREFCLK0P_225
|
||||||
|
set_property -dict {LOC AL8 } [get_ports pcie_refclk_n] ;# MGTREFCLK0N_225
|
||||||
|
set_property -dict {LOC AM17 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n]
|
||||||
|
|
||||||
|
# 100 MHz MGT reference clock
|
||||||
|
create_clock -period 10 -name pcie_refclk [get_ports pcie_refclk_p]
|
||||||
|
|
||||||
|
set_false_path -from [get_ports {pcie_reset_n}]
|
||||||
|
set_input_delay 0 [get_ports {pcie_reset_n}]
|
||||||
|
|
||||||
|
# FMC interface
|
||||||
|
# FMC HPC0 J22
|
||||||
|
#set_property -dict {LOC AY9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[0]"] ;# J22.G9 LA00_P_CC
|
||||||
|
#set_property -dict {LOC BA9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[0]"] ;# J22.G10 LA00_N_CC
|
||||||
|
#set_property -dict {LOC BC10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[1]"] ;# J22.D8 LA01_P_CC
|
||||||
|
#set_property -dict {LOC BD10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[1]"] ;# J22.D9 LA01_N_CC
|
||||||
|
#set_property -dict {LOC BA7 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[2]"] ;# J22.H7 LA02_P
|
||||||
|
#set_property -dict {LOC BB7 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[2]"] ;# J22.H8 LA02_N
|
||||||
|
#set_property -dict {LOC BD8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[3]"] ;# J22.G12 LA03_P
|
||||||
|
#set_property -dict {LOC BD7 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[3]"] ;# J22.G13 LA03_N
|
||||||
|
#set_property -dict {LOC BE8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[4]"] ;# J22.H10 LA04_P
|
||||||
|
#set_property -dict {LOC BE7 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[4]"] ;# J22.H11 LA04_N
|
||||||
|
#set_property -dict {LOC BF12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[5]"] ;# J22.D11 LA05_P
|
||||||
|
#set_property -dict {LOC BF11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[5]"] ;# J22.D12 LA05_N
|
||||||
|
#set_property -dict {LOC BE10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[6]"] ;# J22.C10 LA06_P
|
||||||
|
#set_property -dict {LOC BE9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[6]"] ;# J22.C11 LA06_N
|
||||||
|
#set_property -dict {LOC BD12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[7]"] ;# J22.H13 LA07_P
|
||||||
|
#set_property -dict {LOC BE12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[7]"] ;# J22.H14 LA07_N
|
||||||
|
#set_property -dict {LOC BF10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[8]"] ;# J22.G12 LA08_P
|
||||||
|
#set_property -dict {LOC BF9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[8]"] ;# J22.G13 LA08_N
|
||||||
|
#set_property -dict {LOC BD13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[9]"] ;# J22.D14 LA09_P
|
||||||
|
#set_property -dict {LOC BE13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[9]"] ;# J22.D15 LA09_N
|
||||||
|
#set_property -dict {LOC BE14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[10]"] ;# J22.C14 LA10_P
|
||||||
|
#set_property -dict {LOC BF14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[10]"] ;# J22.C15 LA10_N
|
||||||
|
#set_property -dict {LOC BC11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[11]"] ;# J22.H16 LA11_P
|
||||||
|
#set_property -dict {LOC BD11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[11]"] ;# J22.H17 LA11_N
|
||||||
|
#set_property -dict {LOC BE15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[12]"] ;# J22.G15 LA12_P
|
||||||
|
#set_property -dict {LOC BF15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[12]"] ;# J22.G16 LA12_N
|
||||||
|
#set_property -dict {LOC BA14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[13]"] ;# J22.D17 LA13_P
|
||||||
|
#set_property -dict {LOC BB14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[13]"] ;# J22.D18 LA13_N
|
||||||
|
#set_property -dict {LOC BB13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[14]"] ;# J22.C18 LA14_P
|
||||||
|
#set_property -dict {LOC BB12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[14]"] ;# J22.C19 LA14_N
|
||||||
|
#set_property -dict {LOC AV9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[15]"] ;# J22.H19 LA15_P
|
||||||
|
#set_property -dict {LOC AV8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[15]"] ;# J22.H20 LA15_N
|
||||||
|
#set_property -dict {LOC AY8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[16]"] ;# J22.G18 LA16_P
|
||||||
|
#set_property -dict {LOC AY7 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[16]"] ;# J22.G19 LA16_N
|
||||||
|
#set_property -dict {LOC AV14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[17]"] ;# J22.D20 LA17_P_CC
|
||||||
|
#set_property -dict {LOC AV13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[17]"] ;# J22.D21 LA17_N_CC
|
||||||
|
#set_property -dict {LOC AP13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[18]"] ;# J22.C22 LA18_P_CC
|
||||||
|
#set_property -dict {LOC AR13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[18]"] ;# J22.C23 LA18_N_CC
|
||||||
|
#set_property -dict {LOC AV15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[19]"] ;# J22.H22 LA19_P
|
||||||
|
#set_property -dict {LOC AW15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[19]"] ;# J22.H23 LA19_N
|
||||||
|
#set_property -dict {LOC AY15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[20]"] ;# J22.G21 LA20_P
|
||||||
|
#set_property -dict {LOC AY14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[20]"] ;# J22.G22 LA20_N
|
||||||
|
#set_property -dict {LOC AN16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[21]"] ;# J22.H25 LA21_P
|
||||||
|
#set_property -dict {LOC AP16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[21]"] ;# J22.H26 LA21_N
|
||||||
|
#set_property -dict {LOC AN15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[22]"] ;# J22.G24 LA22_P
|
||||||
|
#set_property -dict {LOC AP15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[22]"] ;# J22.G25 LA22_N
|
||||||
|
#set_property -dict {LOC AT16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[23]"] ;# J22.D23 LA23_P
|
||||||
|
#set_property -dict {LOC AT15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[23]"] ;# J22.D24 LA23_N
|
||||||
|
#set_property -dict {LOC AK15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[24]"] ;# J22.H28 LA24_P
|
||||||
|
#set_property -dict {LOC AL15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[24]"] ;# J22.H29 LA24_N
|
||||||
|
#set_property -dict {LOC AM13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[25]"] ;# J22.G27 LA25_P
|
||||||
|
#set_property -dict {LOC AM12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[25]"] ;# J22.G28 LA25_N
|
||||||
|
#set_property -dict {LOC AL14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[26]"] ;# J22.D26 LA26_P
|
||||||
|
#set_property -dict {LOC AM14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[26]"] ;# J22.D27 LA26_N
|
||||||
|
#set_property -dict {LOC AN14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[27]"] ;# J22.C26 LA27_P
|
||||||
|
#set_property -dict {LOC AN13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[27]"] ;# J22.C27 LA27_N
|
||||||
|
#set_property -dict {LOC AJ13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[28]"] ;# J22.H31 LA28_P
|
||||||
|
#set_property -dict {LOC AJ12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[28]"] ;# J22.H32 LA28_N
|
||||||
|
#set_property -dict {LOC AK14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[29]"] ;# J22.G30 LA29_P
|
||||||
|
#set_property -dict {LOC AK13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[29]"] ;# J22.G31 LA29_N
|
||||||
|
#set_property -dict {LOC AK12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[30]"] ;# J22.H34 LA30_P
|
||||||
|
#set_property -dict {LOC AL12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[30]"] ;# J22.H35 LA30_N
|
||||||
|
#set_property -dict {LOC AP12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[31]"] ;# J22.G33 LA31_P
|
||||||
|
#set_property -dict {LOC AR12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[31]"] ;# J22.G34 LA31_N
|
||||||
|
#set_property -dict {LOC AU11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[32]"] ;# J22.H37 LA32_P
|
||||||
|
#set_property -dict {LOC AV11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[32]"] ;# J22.H38 LA32_N
|
||||||
|
#set_property -dict {LOC AU16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_p[33]"] ;# J22.G36 LA33_P
|
||||||
|
#set_property -dict {LOC AV16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_la_n[33]"] ;# J22.G37 LA33_N
|
||||||
|
|
||||||
|
#set_property -dict {LOC N14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[0]"] ;# J22.F4 HA00_P_CC
|
||||||
|
#set_property -dict {LOC N13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[0]"] ;# J22.F5 HA00_N_CC
|
||||||
|
#set_property -dict {LOC T14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[1]"] ;# J22.E2 HA01_P_CC
|
||||||
|
#set_property -dict {LOC R13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[1]"] ;# J22.E3 HA01_N_CC
|
||||||
|
#set_property -dict {LOC T16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[2]"] ;# J22.K7 HA02_P
|
||||||
|
#set_property -dict {LOC T15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[2]"] ;# J22.K8 HA02_N
|
||||||
|
#set_property -dict {LOC K11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[3]"] ;# J22.J6 HA03_P
|
||||||
|
#set_property -dict {LOC J11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[3]"] ;# J22.J7 HA03_N
|
||||||
|
#set_property -dict {LOC AA13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[4]"] ;# J22.F7 HA04_P
|
||||||
|
#set_property -dict {LOC Y13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[4]"] ;# J22.F8 HA04_N
|
||||||
|
#set_property -dict {LOC AA12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[5]"] ;# J22.E6 HA05_P
|
||||||
|
#set_property -dict {LOC Y12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[5]"] ;# J22.E7 HA05_N
|
||||||
|
#set_property -dict {LOC P15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[6]"] ;# J22.K10 HA06_P
|
||||||
|
#set_property -dict {LOC N15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[6]"] ;# J22.K11 HA06_N
|
||||||
|
#set_property -dict {LOC R12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[7]"] ;# J22.J9 HA07_P
|
||||||
|
#set_property -dict {LOC P12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[7]"] ;# J22.J10 HA07_N
|
||||||
|
#set_property -dict {LOC W12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[8]"] ;# J22.F10 HA08_P
|
||||||
|
#set_property -dict {LOC V12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[8]"] ;# J22.F11 HA08_N
|
||||||
|
#set_property -dict {LOC AA14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[9]"] ;# J22.E9 HA09_P
|
||||||
|
#set_property -dict {LOC Y14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[9]"] ;# J22.E10 HA09_N
|
||||||
|
#set_property -dict {LOC K12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[10]"] ;# J22.K13 HA10_P
|
||||||
|
#set_property -dict {LOC J12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[10]"] ;# J22.K14 HA10_N
|
||||||
|
#set_property -dict {LOC M11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[11]"] ;# J22.J12 HA11_P
|
||||||
|
#set_property -dict {LOC L11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[11]"] ;# J22.J13 HA11_N
|
||||||
|
#set_property -dict {LOC V15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[12]"] ;# J22.F13 HA12_P
|
||||||
|
#set_property -dict {LOC U15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[12]"] ;# J22.F14 HA12_N
|
||||||
|
#set_property -dict {LOC W14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[13]"] ;# J22.E12 HA13_P
|
||||||
|
#set_property -dict {LOC V14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[13]"] ;# J22.E13 HA13_N
|
||||||
|
#set_property -dict {LOC K14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[14]"] ;# J22.J15 HA14_P
|
||||||
|
#set_property -dict {LOC K13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[14]"] ;# J22.J16 HA14_N
|
||||||
|
#set_property -dict {LOC V13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[15]"] ;# J22.F14 HA15_P
|
||||||
|
#set_property -dict {LOC U12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[15]"] ;# J22.F16 HA15_N
|
||||||
|
#set_property -dict {LOC V16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[16]"] ;# J22.E15 HA16_P
|
||||||
|
#set_property -dict {LOC U16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[16]"] ;# J22.E16 HA16_N
|
||||||
|
#set_property -dict {LOC U13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[17]"] ;# J22.K16 HA17_P_CC
|
||||||
|
#set_property -dict {LOC T13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[17]"] ;# J22.K17 HA17_N_CC
|
||||||
|
#set_property -dict {LOC L14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[18]"] ;# J22.J18 HA18_P_CC
|
||||||
|
#set_property -dict {LOC L13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[18]"] ;# J22.J19 HA18_N_CC
|
||||||
|
#set_property -dict {LOC R14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[19]"] ;# J22.F19 HA19_P
|
||||||
|
#set_property -dict {LOC P14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[19]"] ;# J22.F20 HA19_N
|
||||||
|
#set_property -dict {LOC R11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[20]"] ;# J22.E18 HA20_P
|
||||||
|
#set_property -dict {LOC P11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[20]"] ;# J22.E19 HA20_N
|
||||||
|
#set_property -dict {LOC M13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[21]"] ;# J22.K19 HA21_P
|
||||||
|
#set_property -dict {LOC M12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[21]"] ;# J22.K20 HA21_N
|
||||||
|
#set_property -dict {LOC M15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[22]"] ;# J22.J21 HA22_P
|
||||||
|
#set_property -dict {LOC L15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[22]"] ;# J22.J22 HA22_N
|
||||||
|
#set_property -dict {LOC U11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_p[23]"] ;# J22.K22 HA23_P
|
||||||
|
#set_property -dict {LOC T11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_ha_n[23]"] ;# J22.K23 HA23_N
|
||||||
|
|
||||||
|
#set_property -dict {LOC BB9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_clk0_m2c_p"] ;# J22.H4 CLK0_M2C_P
|
||||||
|
#set_property -dict {LOC BB8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_clk0_m2c_n"] ;# J22.H5 CLK0_M2C_N
|
||||||
|
#set_property -dict {LOC AU14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_clk1_m2c_p"] ;# J22.G2 CLK1_M2C_P
|
||||||
|
#set_property -dict {LOC AU13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc0_clk1_m2c_n"] ;# J22.G3 CLK1_M2C_N
|
||||||
|
|
||||||
|
#set_property -dict {LOC AP22 IOSTANDARD LVCMOS18} [get_ports {fmc_hpc0_pg_m2c}] ;# J22.F1 PG_M2C
|
||||||
|
#set_property -dict {LOC AL19 IOSTANDARD LVCMOS18} [get_ports {fmc_hpc0_prsnt_m2c_l}] ;# J22.H2 PRSNT_M2C_L
|
||||||
|
|
||||||
|
#set_property -dict {LOC G5 } [get_ports {fmc_hpc0_dp_c2m_p[0]}] ;# MGTHTXP0_230 GTHE3_CHANNEL_X0Y24 / GTHE3_COMMON_X0Y6 from J22.C2 DP0_C2M_P
|
||||||
|
#set_property -dict {LOC G4 } [get_ports {fmc_hpc0_dp_c2m_n[0]}] ;# MGTHTXN0_230 GTHE3_CHANNEL_X0Y24 / GTHE3_COMMON_X0Y6 from J22.C3 DP0_C2M_N
|
||||||
|
#set_property -dict {LOC K2 } [get_ports {fmc_hpc0_dp_m2c_p[0]}] ;# MGTHRXP0_230 GTHE3_CHANNEL_X0Y24 / GTHE3_COMMON_X0Y6 from J22.C6 DP0_M2C_P
|
||||||
|
#set_property -dict {LOC K1 } [get_ports {fmc_hpc0_dp_m2c_n[0]}] ;# MGTHRXN0_230 GTHE3_CHANNEL_X0Y24 / GTHE3_COMMON_X0Y6 from J22.C7 DP0_M2C_N
|
||||||
|
#set_property -dict {LOC F7 } [get_ports {fmc_hpc0_dp_c2m_p[1]}] ;# MGTHTXP1_230 GTHE3_CHANNEL_X0Y25 / GTHE3_COMMON_X0Y6 from J22.A22 DP1_C2M_P
|
||||||
|
#set_property -dict {LOC F6 } [get_ports {fmc_hpc0_dp_c2m_n[1]}] ;# MGTHTXN1_230 GTHE3_CHANNEL_X0Y25 / GTHE3_COMMON_X0Y6 from J22.A23 DP1_C2M_N
|
||||||
|
#set_property -dict {LOC H2 } [get_ports {fmc_hpc0_dp_m2c_p[1]}] ;# MGTHRXP1_230 GTHE3_CHANNEL_X0Y25 / GTHE3_COMMON_X0Y6 from J22.A2 DP1_M2C_P
|
||||||
|
#set_property -dict {LOC H1 } [get_ports {fmc_hpc0_dp_m2c_n[1]}] ;# MGTHRXN1_230 GTHE3_CHANNEL_X0Y25 / GTHE3_COMMON_X0Y6 from J22.A3 DP1_M2C_N
|
||||||
|
#set_property -dict {LOC E5 } [get_ports {fmc_hpc0_dp_c2m_p[2]}] ;# MGTHTXP2_230 GTHE3_CHANNEL_X0Y26 / GTHE3_COMMON_X0Y6 from J22.A26 DP2_C2M_P
|
||||||
|
#set_property -dict {LOC E4 } [get_ports {fmc_hpc0_dp_c2m_n[2]}] ;# MGTHTXN2_230 GTHE3_CHANNEL_X0Y26 / GTHE3_COMMON_X0Y6 from J22.A27 DP2_C2M_N
|
||||||
|
#set_property -dict {LOC F2 } [get_ports {fmc_hpc0_dp_m2c_p[2]}] ;# MGTHRXP2_230 GTHE3_CHANNEL_X0Y26 / GTHE3_COMMON_X0Y6 from J22.A6 DP2_M2C_P
|
||||||
|
#set_property -dict {LOC F1 } [get_ports {fmc_hpc0_dp_m2c_n[2]}] ;# MGTHRXN2_230 GTHE3_CHANNEL_X0Y26 / GTHE3_COMMON_X0Y6 from J22.A7 DP2_M2C_N
|
||||||
|
#set_property -dict {LOC C5 } [get_ports {fmc_hpc0_dp_c2m_p[3]}] ;# MGTHTXP3_230 GTHE3_CHANNEL_X0Y27 / GTHE3_COMMON_X0Y6 from J22.A30 DP3_C2M_P
|
||||||
|
#set_property -dict {LOC C4 } [get_ports {fmc_hpc0_dp_c2m_n[3]}] ;# MGTHTXN3_230 GTHE3_CHANNEL_X0Y27 / GTHE3_COMMON_X0Y6 from J22.A31 DP3_C2M_N
|
||||||
|
#set_property -dict {LOC D2 } [get_ports {fmc_hpc0_dp_m2c_p[3]}] ;# MGTHRXP3_230 GTHE3_CHANNEL_X0Y27 / GTHE3_COMMON_X0Y6 from J22.A10 DP3_M2C_P
|
||||||
|
#set_property -dict {LOC D1 } [get_ports {fmc_hpc0_dp_m2c_n[3]}] ;# MGTHRXN3_230 GTHE3_CHANNEL_X0Y27 / GTHE3_COMMON_X0Y6 from J22.A11 DP3_M2C_N
|
||||||
|
|
||||||
|
#set_property -dict {LOC L5 } [get_ports {fmc_hpc0_dp_c2m_p[4]}] ;# MGTHTXP0_229 GTHE3_CHANNEL_X0Y20 / GTHE3_COMMON_X0Y5 from J22.A34 DP4_C2M_P
|
||||||
|
#set_property -dict {LOC L4 } [get_ports {fmc_hpc0_dp_c2m_n[4]}] ;# MGTHTXN0_229 GTHE3_CHANNEL_X0Y20 / GTHE3_COMMON_X0Y5 from J22.A35 DP4_C2M_N
|
||||||
|
#set_property -dict {LOC T2 } [get_ports {fmc_hpc0_dp_m2c_p[4]}] ;# MGTHRXP0_229 GTHE3_CHANNEL_X0Y20 / GTHE3_COMMON_X0Y5 from J22.A14 DP4_M2C_P
|
||||||
|
#set_property -dict {LOC T1 } [get_ports {fmc_hpc0_dp_m2c_n[4]}] ;# MGTHRXN0_229 GTHE3_CHANNEL_X0Y20 / GTHE3_COMMON_X0Y5 from J22.A15 DP4_M2C_N
|
||||||
|
#set_property -dict {LOC K7 } [get_ports {fmc_hpc0_dp_c2m_p[5]}] ;# MGTHTXP1_229 GTHE3_CHANNEL_X0Y21 / GTHE3_COMMON_X0Y5 from J22.A38 DP5_C2M_P
|
||||||
|
#set_property -dict {LOC K6 } [get_ports {fmc_hpc0_dp_c2m_n[5]}] ;# MGTHTXN1_229 GTHE3_CHANNEL_X0Y21 / GTHE3_COMMON_X0Y5 from J22.A39 DP5_C2M_N
|
||||||
|
#set_property -dict {LOC R4 } [get_ports {fmc_hpc0_dp_m2c_p[5]}] ;# MGTHRXP1_229 GTHE3_CHANNEL_X0Y21 / GTHE3_COMMON_X0Y5 from J22.A18 DP5_M2C_P
|
||||||
|
#set_property -dict {LOC R3 } [get_ports {fmc_hpc0_dp_m2c_n[5]}] ;# MGTHRXN1_229 GTHE3_CHANNEL_X0Y21 / GTHE3_COMMON_X0Y5 from J22.A19 DP5_M2C_N
|
||||||
|
#set_property -dict {LOC J5 } [get_ports {fmc_hpc0_dp_c2m_p[6]}] ;# MGTHTXP2_229 GTHE3_CHANNEL_X0Y22 / GTHE3_COMMON_X0Y5 from J22.B36 DP6_C2M_P
|
||||||
|
#set_property -dict {LOC J4 } [get_ports {fmc_hpc0_dp_c2m_n[6]}] ;# MGTHTXN2_229 GTHE3_CHANNEL_X0Y22 / GTHE3_COMMON_X0Y5 from J22.B37 DP6_C2M_N
|
||||||
|
#set_property -dict {LOC P2 } [get_ports {fmc_hpc0_dp_m2c_p[6]}] ;# MGTHRXP2_229 GTHE3_CHANNEL_X0Y22 / GTHE3_COMMON_X0Y5 from J22.B16 DP6_M2C_P
|
||||||
|
#set_property -dict {LOC P1 } [get_ports {fmc_hpc0_dp_m2c_n[6]}] ;# MGTHRXN2_229 GTHE3_CHANNEL_X0Y22 / GTHE3_COMMON_X0Y5 from J22.B17 DP6_M2C_N
|
||||||
|
#set_property -dict {LOC H7 } [get_ports {fmc_hpc0_dp_c2m_p[7]}] ;# MGTHTXP3_229 GTHE3_CHANNEL_X0Y23 / GTHE3_COMMON_X0Y5 from J22.B32 DP7_C2M_P
|
||||||
|
#set_property -dict {LOC H6 } [get_ports {fmc_hpc0_dp_c2m_n[7]}] ;# MGTHTXN3_229 GTHE3_CHANNEL_X0Y23 / GTHE3_COMMON_X0Y5 from J22.B33 DP7_C2M_N
|
||||||
|
#set_property -dict {LOC M2 } [get_ports {fmc_hpc0_dp_m2c_p[7]}] ;# MGTHRXP3_229 GTHE3_CHANNEL_X0Y23 / GTHE3_COMMON_X0Y5 from J22.B12 DP7_M2C_P
|
||||||
|
#set_property -dict {LOC M1 } [get_ports {fmc_hpc0_dp_m2c_n[7]}] ;# MGTHRXN3_229 GTHE3_CHANNEL_X0Y23 / GTHE3_COMMON_X0Y5 from J22.B13 DP7_M2C_N
|
||||||
|
#set_property -dict {LOC R9 } [get_ports fmc_hpc0_mgt_refclk_0_p] ;# MGTREFCLK0P_229 from J22.D4 GBTCLK0_M2C_P
|
||||||
|
#set_property -dict {LOC R8 } [get_ports fmc_hpc0_mgt_refclk_0_n] ;# MGTREFCLK0N_229 from J22.D5 GBTCLK0_M2C_N
|
||||||
|
#set_property -dict {LOC N9 } [get_ports fmc_hpc0_mgt_refclk_1_p] ;# MGTREFCLK1P_229 from J22.B20 GBTCLK1_M2C_P
|
||||||
|
#set_property -dict {LOC N8 } [get_ports fmc_hpc0_mgt_refclk_1_n] ;# MGTREFCLK1N_229 from J22.B21 GBTCLK1_M2C_N
|
||||||
|
|
||||||
|
# reference clock
|
||||||
|
#create_clock -period 6.400 -name fmc_hpc0_mgt_refclk_0 [get_ports fmc_hpc0_mgt_refclk_0_p]
|
||||||
|
#create_clock -period 6.400 -name fmc_hpc0_mgt_refclk_1 [get_ports fmc_hpc0_mgt_refclk_1_p]
|
||||||
|
|
||||||
|
#set_property -dict {LOC V7 } [get_ports {fmc_hpc0_dp_c2m_p[8]}] ;# MGTHTXP0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4 from J22.B28 DP8_C2M_P
|
||||||
|
#set_property -dict {LOC V6 } [get_ports {fmc_hpc0_dp_c2m_n[8]}] ;# MGTHTXN0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4 from J22.B29 DP8_C2M_N
|
||||||
|
#set_property -dict {LOC Y2 } [get_ports {fmc_hpc0_dp_m2c_p[8]}] ;# MGTHRXP0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4 from J22.B8 DP8_M2C_P
|
||||||
|
#set_property -dict {LOC Y1 } [get_ports {fmc_hpc0_dp_m2c_n[8]}] ;# MGTHRXN0_228 GTHE3_CHANNEL_X0Y16 / GTHE3_COMMON_X0Y4 from J22.B9 DP8_M2C_N
|
||||||
|
#set_property -dict {LOC T7 } [get_ports {fmc_hpc0_dp_c2m_p[9]}] ;# MGTHTXP1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4 from J22.B24 DP9_C2M_P
|
||||||
|
#set_property -dict {LOC T6 } [get_ports {fmc_hpc0_dp_c2m_n[9]}] ;# MGTHTXN1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4 from J22.B25 DP9_C2M_N
|
||||||
|
#set_property -dict {LOC W4 } [get_ports {fmc_hpc0_dp_m2c_p[9]}] ;# MGTHRXP1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4 from J22.B4 DP9_M2C_P
|
||||||
|
#set_property -dict {LOC W3 } [get_ports {fmc_hpc0_dp_m2c_n[9]}] ;# MGTHRXN1_228 GTHE3_CHANNEL_X0Y17 / GTHE3_COMMON_X0Y4 from J22.B5 DP9_M2C_N
|
||||||
|
#set_property -dict {LOC W9 } [get_ports fmc_hpc0_mgt_refclk_2_p] ;# MGTREFCLK0P_228 from from J87 P1
|
||||||
|
#set_property -dict {LOC W8 } [get_ports fmc_hpc0_mgt_refclk_2_n] ;# MGTREFCLK0N_228 from from J87 P2
|
||||||
|
|
||||||
|
# reference clock
|
||||||
|
#create_clock -period 6.400 -name fmc_hpc0_mgt_refclk_2 [get_ports fmc_hpc0_mgt_refclk_2_p]
|
||||||
|
|
||||||
|
# FMC HPC1 J2
|
||||||
|
#set_property -dict {LOC T33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[0]"] ;# J2.G9 LA00_P_CC
|
||||||
|
#set_property -dict {LOC R33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[0]"] ;# J2.G10 LA00_N_CC
|
||||||
|
#set_property -dict {LOC P35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[1]"] ;# J2.D8 LA01_P_CC
|
||||||
|
#set_property -dict {LOC P36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[1]"] ;# J2.D9 LA01_N_CC
|
||||||
|
#set_property -dict {LOC N33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[2]"] ;# J2.H7 LA02_P
|
||||||
|
#set_property -dict {LOC M33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[2]"] ;# J2.H8 LA02_N
|
||||||
|
#set_property -dict {LOC N34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[3]"] ;# J2.G12 LA03_P
|
||||||
|
#set_property -dict {LOC N35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[3]"] ;# J2.G13 LA03_N
|
||||||
|
#set_property -dict {LOC M37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[4]"] ;# J2.H10 LA04_P
|
||||||
|
#set_property -dict {LOC L38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[4]"] ;# J2.H11 LA04_N
|
||||||
|
#set_property -dict {LOC N38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[5]"] ;# J2.D11 LA05_P
|
||||||
|
#set_property -dict {LOC M38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[5]"] ;# J2.D12 LA05_N
|
||||||
|
#set_property -dict {LOC P37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[6]"] ;# J2.C10 LA06_P
|
||||||
|
#set_property -dict {LOC N37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[6]"] ;# J2.C11 LA06_N
|
||||||
|
#set_property -dict {LOC L34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[7]"] ;# J2.H13 LA07_P
|
||||||
|
#set_property -dict {LOC K34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[7]"] ;# J2.H14 LA07_N
|
||||||
|
#set_property -dict {LOC M35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[8]"] ;# J2.G12 LA08_P
|
||||||
|
#set_property -dict {LOC L35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[8]"] ;# J2.G13 LA08_N
|
||||||
|
#set_property -dict {LOC M36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[9]"] ;# J2.D14 LA09_P
|
||||||
|
#set_property -dict {LOC L36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[9]"] ;# J2.D15 LA09_N
|
||||||
|
#set_property -dict {LOC N32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[10]"] ;# J2.C14 LA10_P
|
||||||
|
#set_property -dict {LOC M32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[10]"] ;# J2.C15 LA10_N
|
||||||
|
#set_property -dict {LOC Y31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[11]"] ;# J2.H16 LA11_P
|
||||||
|
#set_property -dict {LOC W31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[11]"] ;# J2.H17 LA11_N
|
||||||
|
#set_property -dict {LOC R31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[12]"] ;# J2.G15 LA12_P
|
||||||
|
#set_property -dict {LOC P31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[12]"] ;# J2.G16 LA12_N
|
||||||
|
#set_property -dict {LOC T30 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[13]"] ;# J2.D17 LA13_P
|
||||||
|
#set_property -dict {LOC T31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[13]"] ;# J2.D18 LA13_N
|
||||||
|
#set_property -dict {LOC L33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[14]"] ;# J2.C18 LA14_P
|
||||||
|
#set_property -dict {LOC K33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[14]"] ;# J2.C19 LA14_N
|
||||||
|
#set_property -dict {LOC T34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[15]"] ;# J2.H19 LA15_P
|
||||||
|
#set_property -dict {LOC T35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[15]"] ;# J2.H20 LA15_N
|
||||||
|
#set_property -dict {LOC U31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[16]"] ;# J2.G18 LA16_P
|
||||||
|
#set_property -dict {LOC U32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[16]"] ;# J2.G19 LA16_N
|
||||||
|
#set_property -dict {LOC AJ32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[17]"] ;# J2.D20 LA17_P_CC
|
||||||
|
#set_property -dict {LOC AK32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[17]"] ;# J2.D21 LA17_N_CC
|
||||||
|
#set_property -dict {LOC AL32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[18]"] ;# J2.C22 LA18_P_CC
|
||||||
|
#set_property -dict {LOC AM32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[18]"] ;# J2.C23 LA18_N_CC
|
||||||
|
#set_property -dict {LOC AT39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[19]"] ;# J2.H22 LA19_P
|
||||||
|
#set_property -dict {LOC AT40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[19]"] ;# J2.H23 LA19_N
|
||||||
|
#set_property -dict {LOC AR37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[20]"] ;# J2.G21 LA20_P
|
||||||
|
#set_property -dict {LOC AT37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[20]"] ;# J2.G22 LA20_N
|
||||||
|
#set_property -dict {LOC AT35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[21]"] ;# J2.H25 LA21_P
|
||||||
|
#set_property -dict {LOC AT36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[21]"] ;# J2.H26 LA21_N
|
||||||
|
#set_property -dict {LOC AL30 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[22]"] ;# J2.G24 LA22_P
|
||||||
|
#set_property -dict {LOC AL31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[22]"] ;# J2.G25 LA22_N
|
||||||
|
#set_property -dict {LOC AN33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[23]"] ;# J2.D23 LA23_P
|
||||||
|
#set_property -dict {LOC AP33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[23]"] ;# J2.D24 LA23_N
|
||||||
|
#set_property -dict {LOC AM36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[24]"] ;# J2.H28 LA24_P
|
||||||
|
#set_property -dict {LOC AN36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[24]"] ;# J2.H29 LA24_N
|
||||||
|
#set_property -dict {LOC AP36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[25]"] ;# J2.G27 LA25_P
|
||||||
|
#set_property -dict {LOC AP37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[25]"] ;# J2.G28 LA25_N
|
||||||
|
#set_property -dict {LOC AL29 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[26]"] ;# J2.D26 LA26_P
|
||||||
|
#set_property -dict {LOC AM29 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[26]"] ;# J2.D27 LA26_N
|
||||||
|
#set_property -dict {LOC AP35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[27]"] ;# J2.C26 LA27_P
|
||||||
|
#set_property -dict {LOC AR35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[27]"] ;# J2.C27 LA27_N
|
||||||
|
#set_property -dict {LOC AL35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[28]"] ;# J2.H31 LA28_P
|
||||||
|
#set_property -dict {LOC AL36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[28]"] ;# J2.H32 LA28_N
|
||||||
|
#set_property -dict {LOC AP38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[29]"] ;# J2.G30 LA29_P
|
||||||
|
#set_property -dict {LOC AR38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[29]"] ;# J2.G31 LA29_N
|
||||||
|
#set_property -dict {LOC AJ30 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[30]"] ;# J2.H34 LA30_P
|
||||||
|
#set_property -dict {LOC AJ31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[30]"] ;# J2.H35 LA30_N
|
||||||
|
#set_property -dict {LOC AN34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[31]"] ;# J2.G33 LA31_P
|
||||||
|
#set_property -dict {LOC AN35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[31]"] ;# J2.G34 LA31_N
|
||||||
|
#set_property -dict {LOC AG31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[32]"] ;# J2.H37 LA32_P
|
||||||
|
#set_property -dict {LOC AH31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[32]"] ;# J2.H38 LA32_N
|
||||||
|
#set_property -dict {LOC AG32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_p[33]"] ;# J2.G36 LA33_P
|
||||||
|
#set_property -dict {LOC AG33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_la_n[33]"] ;# J2.G37 LA33_N
|
||||||
|
|
||||||
|
#set_property -dict {LOC R32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_clk0_m2c_p"] ;# J2.H4 CLK0_M2C_P
|
||||||
|
#set_property -dict {LOC P32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_clk0_m2c_n"] ;# J2.H5 CLK0_M2C_N
|
||||||
|
#set_property -dict {LOC AK34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_clk1_m2c_p"] ;# J2.G2 CLK1_M2C_P
|
||||||
|
#set_property -dict {LOC AL34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports "fmc_hpc1_clk1_m2c_n"] ;# J2.G3 CLK1_M2C_N
|
||||||
|
|
||||||
|
#set_property -dict {LOC AU24 IOSTANDARD LVCMOS18} [get_ports {fmc_hpc1_pg_m2c}] ;# J2.F1 PG_M2C
|
||||||
|
#set_property -dict {LOC BD23 IOSTANDARD LVCMOS18} [get_ports {fmc_hpc1_prsnt_m2c_l}] ;# J2.H2 PRSNT_M2C_L
|
||||||
|
|
||||||
|
#set_property -dict {LOC AN5 } [get_ports {fmc_hpc1_dp_c2m_p[0]}] ;# MGTHTXP0_226 GTHE3_CHANNEL_X0Y8 / GTHE3_COMMON_X0Y2 from J2.C2 DP0_C2M_P
|
||||||
|
#set_property -dict {LOC AN4 } [get_ports {fmc_hpc1_dp_c2m_n[0]}] ;# MGTHTXN0_226 GTHE3_CHANNEL_X0Y8 / GTHE3_COMMON_X0Y2 from J2.C3 DP0_C2M_N
|
||||||
|
#set_property -dict {LOC AH2 } [get_ports {fmc_hpc1_dp_m2c_p[0]}] ;# MGTHRXP0_226 GTHE3_CHANNEL_X0Y8 / GTHE3_COMMON_X0Y2 from J2.C6 DP0_M2C_P
|
||||||
|
#set_property -dict {LOC AH1 } [get_ports {fmc_hpc1_dp_m2c_n[0]}] ;# MGTHRXN0_226 GTHE3_CHANNEL_X0Y8 / GTHE3_COMMON_X0Y2 from J2.C7 DP0_M2C_N
|
||||||
|
#set_property -dict {LOC AM7 } [get_ports {fmc_hpc1_dp_c2m_p[1]}] ;# MGTHTXP1_226 GTHE3_CHANNEL_X0Y9 / GTHE3_COMMON_X0Y2 from J2.A22 DP1_C2M_P
|
||||||
|
#set_property -dict {LOC AM6 } [get_ports {fmc_hpc1_dp_c2m_n[1]}] ;# MGTHTXN1_226 GTHE3_CHANNEL_X0Y9 / GTHE3_COMMON_X0Y2 from J2.A23 DP1_C2M_N
|
||||||
|
#set_property -dict {LOC AG4 } [get_ports {fmc_hpc1_dp_m2c_p[1]}] ;# MGTHRXP1_226 GTHE3_CHANNEL_X0Y9 / GTHE3_COMMON_X0Y2 from J2.A2 DP1_M2C_P
|
||||||
|
#set_property -dict {LOC AG3 } [get_ports {fmc_hpc1_dp_m2c_n[1]}] ;# MGTHRXN1_226 GTHE3_CHANNEL_X0Y9 / GTHE3_COMMON_X0Y2 from J2.A3 DP1_M2C_N
|
||||||
|
#set_property -dict {LOC AK7 } [get_ports {fmc_hpc1_dp_c2m_p[2]}] ;# MGTHTXP2_226 GTHE3_CHANNEL_X0Y10 / GTHE3_COMMON_X0Y2 from J2.A26 DP2_C2M_P
|
||||||
|
#set_property -dict {LOC AK6 } [get_ports {fmc_hpc1_dp_c2m_n[2]}] ;# MGTHTXN2_226 GTHE3_CHANNEL_X0Y10 / GTHE3_COMMON_X0Y2 from J2.A27 DP2_C2M_N
|
||||||
|
#set_property -dict {LOC AF2 } [get_ports {fmc_hpc1_dp_m2c_p[2]}] ;# MGTHRXP2_226 GTHE3_CHANNEL_X0Y10 / GTHE3_COMMON_X0Y2 from J2.A6 DP2_M2C_P
|
||||||
|
#set_property -dict {LOC AF1 } [get_ports {fmc_hpc1_dp_m2c_n[2]}] ;# MGTHRXN2_226 GTHE3_CHANNEL_X0Y10 / GTHE3_COMMON_X0Y2 from J2.A7 DP2_M2C_N
|
||||||
|
#set_property -dict {LOC AH7 } [get_ports {fmc_hpc1_dp_c2m_p[3]}] ;# MGTHTXP3_226 GTHE3_CHANNEL_X0Y11 / GTHE3_COMMON_X0Y2 from J2.A30 DP3_C2M_P
|
||||||
|
#set_property -dict {LOC AH6 } [get_ports {fmc_hpc1_dp_c2m_n[3]}] ;# MGTHTXN3_226 GTHE3_CHANNEL_X0Y11 / GTHE3_COMMON_X0Y2 from J2.A31 DP3_C2M_N
|
||||||
|
#set_property -dict {LOC AE4 } [get_ports {fmc_hpc1_dp_m2c_p[3]}] ;# MGTHRXP3_226 GTHE3_CHANNEL_X0Y11 / GTHE3_COMMON_X0Y2 from J2.A10 DP3_M2C_P
|
||||||
|
#set_property -dict {LOC AE3 } [get_ports {fmc_hpc1_dp_m2c_n[3]}] ;# MGTHRXN3_226 GTHE3_CHANNEL_X0Y11 / GTHE3_COMMON_X0Y2 from J2.A11 DP3_M2C_N
|
||||||
|
|
||||||
|
#set_property -dict {LOC AF7 } [get_ports {fmc_hpc1_dp_c2m_p[4]}] ;# MGTHTXP0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3 from J2.A34 DP4_C2M_P
|
||||||
|
#set_property -dict {LOC AF6 } [get_ports {fmc_hpc1_dp_c2m_n[4]}] ;# MGTHTXN0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3 from J2.A35 DP4_C2M_N
|
||||||
|
#set_property -dict {LOC AD2 } [get_ports {fmc_hpc1_dp_m2c_p[4]}] ;# MGTHRXP0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3 from J2.A14 DP4_M2C_P
|
||||||
|
#set_property -dict {LOC AD1 } [get_ports {fmc_hpc1_dp_m2c_n[4]}] ;# MGTHRXN0_227 GTHE3_CHANNEL_X0Y12 / GTHE3_COMMON_X0Y3 from J2.A15 DP4_M2C_N
|
||||||
|
#set_property -dict {LOC AD7 } [get_ports {fmc_hpc1_dp_c2m_p[5]}] ;# MGTHTXP1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3 from J2.A38 DP5_C2M_P
|
||||||
|
#set_property -dict {LOC AD6 } [get_ports {fmc_hpc1_dp_c2m_n[5]}] ;# MGTHTXN1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3 from J2.A39 DP5_C2M_N
|
||||||
|
#set_property -dict {LOC AC4 } [get_ports {fmc_hpc1_dp_m2c_p[5]}] ;# MGTHRXP1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3 from J2.A18 DP5_M2C_P
|
||||||
|
#set_property -dict {LOC AC3 } [get_ports {fmc_hpc1_dp_m2c_n[5]}] ;# MGTHRXN1_227 GTHE3_CHANNEL_X0Y13 / GTHE3_COMMON_X0Y3 from J2.A19 DP5_M2C_N
|
||||||
|
#set_property -dict {LOC AB7 } [get_ports {fmc_hpc1_dp_c2m_p[6]}] ;# MGTHTXP2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3 from J2.B36 DP6_C2M_P
|
||||||
|
#set_property -dict {LOC AB6 } [get_ports {fmc_hpc1_dp_c2m_n[6]}] ;# MGTHTXN2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3 from J2.B37 DP6_C2M_N
|
||||||
|
#set_property -dict {LOC AB2 } [get_ports {fmc_hpc1_dp_m2c_p[6]}] ;# MGTHRXP2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3 from J2.B16 DP6_M2C_P
|
||||||
|
#set_property -dict {LOC AB1 } [get_ports {fmc_hpc1_dp_m2c_n[6]}] ;# MGTHRXN2_227 GTHE3_CHANNEL_X0Y14 / GTHE3_COMMON_X0Y3 from J2.B17 DP6_M2C_N
|
||||||
|
#set_property -dict {LOC Y7 } [get_ports {fmc_hpc1_dp_c2m_p[7]}] ;# MGTHTXP3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3 from J2.B32 DP7_C2M_P
|
||||||
|
#set_property -dict {LOC Y6 } [get_ports {fmc_hpc1_dp_c2m_n[7]}] ;# MGTHTXN3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3 from J2.B33 DP7_C2M_N
|
||||||
|
#set_property -dict {LOC AA4 } [get_ports {fmc_hpc1_dp_m2c_p[7]}] ;# MGTHRXP3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3 from J2.B12 DP7_M2C_P
|
||||||
|
#set_property -dict {LOC AA3 } [get_ports {fmc_hpc1_dp_m2c_n[7]}] ;# MGTHRXN3_227 GTHE3_CHANNEL_X0Y15 / GTHE3_COMMON_X0Y3 from J2.B13 DP7_M2C_N
|
||||||
|
#set_property -dict {LOC AC9 } [get_ports fmc_hpc1_mgt_refclk_0_p] ;# MGTREFCLK0P_227 from J2.D4 GBTCLK0_M2C_P
|
||||||
|
#set_property -dict {LOC AC8 } [get_ports fmc_hpc1_mgt_refclk_0_n] ;# MGTREFCLK0N_227 from J2.D5 GBTCLK0_M2C_N
|
||||||
|
#set_property -dict {LOC AA9 } [get_ports fmc_hpc1_mgt_refclk_1_p] ;# MGTREFCLK1P_227 from J2.B20 GBTCLK1_M2C_P
|
||||||
|
#set_property -dict {LOC AA8 } [get_ports fmc_hpc1_mgt_refclk_1_n] ;# MGTREFCLK1N_227 from J2.B21 GBTCLK1_M2C_N
|
||||||
|
|
||||||
|
# reference clock
|
||||||
|
#create_clock -period 6.400 -name fmc_hpc0_mgt_refclk_0 [get_ports fmc_hpc0_mgt_refclk_0_p]
|
||||||
|
#create_clock -period 6.400 -name fmc_hpc0_mgt_refclk_1 [get_ports fmc_hpc0_mgt_refclk_1_p]
|
||||||
|
|
||||||
|
#set_property -dict {LOC P7 } [get_ports {fmc_hpc1_dp_c2m_p[8]}] ;# MGTHTXP2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J2.B28 DP8_C2M_P
|
||||||
|
#set_property -dict {LOC P6 } [get_ports {fmc_hpc1_dp_c2m_n[8]}] ;# MGTHTXN2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J2.B29 DP8_C2M_N
|
||||||
|
#set_property -dict {LOC V2 } [get_ports {fmc_hpc1_dp_m2c_p[8]}] ;# MGTHRXP2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J2.B8 DP8_M2C_P
|
||||||
|
#set_property -dict {LOC V1 } [get_ports {fmc_hpc1_dp_m2c_n[8]}] ;# MGTHRXN2_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J2.B9 DP8_M2C_N
|
||||||
|
#set_property -dict {LOC M7 } [get_ports {fmc_hpc1_dp_c2m_p[9]}] ;# MGTHTXP3_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J2.B24 DP9_C2M_P
|
||||||
|
#set_property -dict {LOC M6 } [get_ports {fmc_hpc1_dp_c2m_n[9]}] ;# MGTHTXN3_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J2.B25 DP9_C2M_N
|
||||||
|
#set_property -dict {LOC U4 } [get_ports {fmc_hpc1_dp_m2c_p[9]}] ;# MGTHRXP3_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J2.B4 DP9_M2C_P
|
||||||
|
#set_property -dict {LOC U3 } [get_ports {fmc_hpc1_dp_m2c_n[9]}] ;# MGTHRXN3_228 GTHE3_CHANNEL_X0Y18 / GTHE3_COMMON_X0Y4 from J2.B5 DP9_M2C_N
|
||||||
|
#set_property -dict {LOC W9 } [get_ports fmc_hpc1_mgt_refclk_2_p] ;# MGTREFCLK0P_228 from from J87 P1
|
||||||
|
#set_property -dict {LOC W8 } [get_ports fmc_hpc1_mgt_refclk_2_n] ;# MGTREFCLK0N_228 from from J87 P2
|
||||||
|
|
||||||
|
# reference clock
|
||||||
|
#create_clock -period 6.400 -name fmc_hpc1_mgt_refclk_2 [get_ports fmc_hpc1_mgt_refclk_2_p]
|
||||||
|
|
||||||
|
# DDR4 C1
|
||||||
|
# 5x MT40A256M16GE-075E
|
||||||
|
#set_property -dict {LOC C30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}]
|
||||||
|
#set_property -dict {LOC D32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}]
|
||||||
|
#set_property -dict {LOC B30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}]
|
||||||
|
#set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}]
|
||||||
|
#set_property -dict {LOC E32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}]
|
||||||
|
#set_property -dict {LOC A29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}]
|
||||||
|
#set_property -dict {LOC C29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}]
|
||||||
|
#set_property -dict {LOC E29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}]
|
||||||
|
#set_property -dict {LOC A30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}]
|
||||||
|
#set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}]
|
||||||
|
#set_property -dict {LOC A31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}]
|
||||||
|
#set_property -dict {LOC A33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}]
|
||||||
|
#set_property -dict {LOC F29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}]
|
||||||
|
#set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}]
|
||||||
|
#set_property -dict {LOC D29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}]
|
||||||
|
#set_property -dict {LOC B31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}]
|
||||||
|
#set_property -dict {LOC B33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}]
|
||||||
|
#set_property -dict {LOC G30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}]
|
||||||
|
#set_property -dict {LOC F30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}]
|
||||||
|
#set_property -dict {LOC F33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}]
|
||||||
|
#set_property -dict {LOC E31 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t}]
|
||||||
|
#set_property -dict {LOC D31 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c}]
|
||||||
|
#set_property -dict {LOC K29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}]
|
||||||
|
#set_property -dict {LOC D30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}]
|
||||||
|
#set_property -dict {LOC E33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}]
|
||||||
|
#set_property -dict {LOC J31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}]
|
||||||
|
#set_property -dict {LOC R29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}]
|
||||||
|
#set_property -dict {LOC M28 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}]
|
||||||
|
#set_property -dict {LOC J40 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_alert_n}]
|
||||||
|
|
||||||
|
#set_property -dict {LOC J37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] ;# U60.G2 DQL0
|
||||||
|
#set_property -dict {LOC H40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] ;# U60.F7 DQL1
|
||||||
|
#set_property -dict {LOC F38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] ;# U60.H3 DQL2
|
||||||
|
#set_property -dict {LOC H39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] ;# U60.H7 DQL3
|
||||||
|
#set_property -dict {LOC K37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] ;# U60.H2 DQL4
|
||||||
|
#set_property -dict {LOC G40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] ;# U60.H8 DQL5
|
||||||
|
#set_property -dict {LOC F39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] ;# U60.J3 DQL6
|
||||||
|
#set_property -dict {LOC F40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] ;# U60.J7 DQL7
|
||||||
|
#set_property -dict {LOC F36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] ;# U60.A3 DQU0
|
||||||
|
#set_property -dict {LOC J36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] ;# U60.B8 DQU1
|
||||||
|
#set_property -dict {LOC F35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] ;# U60.C3 DQU2
|
||||||
|
#set_property -dict {LOC J35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] ;# U60.C7 DQU3
|
||||||
|
#set_property -dict {LOC G37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] ;# U60.C2 DQU4
|
||||||
|
#set_property -dict {LOC H35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] ;# U60.C8 DQU5
|
||||||
|
#set_property -dict {LOC G36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] ;# U60.D3 DQU6
|
||||||
|
#set_property -dict {LOC H37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] ;# U60.D7 DQU7
|
||||||
|
#set_property -dict {LOC H38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] ;# U60.G3 DQSL_T
|
||||||
|
#set_property -dict {LOC G38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] ;# U60.F3 DQSL_C
|
||||||
|
#set_property -dict {LOC H34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] ;# U60.B7 DQSU_T
|
||||||
|
#set_property -dict {LOC G35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] ;# U60.A7 DQSU_C
|
||||||
|
#set_property -dict {LOC J39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[0]}] ;# U60.E7 DML_B/DBIL_B
|
||||||
|
#set_property -dict {LOC F34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[1]}] ;# U60.E2 DMU_B/DBIU_B
|
||||||
|
|
||||||
|
#set_property -dict {LOC C39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] ;# U61.G2 DQL0
|
||||||
|
#set_property -dict {LOC A38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] ;# U61.F7 DQL1
|
||||||
|
#set_property -dict {LOC B40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] ;# U61.H3 DQL2
|
||||||
|
#set_property -dict {LOC D40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] ;# U61.H7 DQL3
|
||||||
|
#set_property -dict {LOC E38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] ;# U61.H2 DQL4
|
||||||
|
#set_property -dict {LOC B38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] ;# U61.H8 DQL5
|
||||||
|
#set_property -dict {LOC E37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] ;# U61.J3 DQL6
|
||||||
|
#set_property -dict {LOC C40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] ;# U61.J7 DQL7
|
||||||
|
#set_property -dict {LOC C34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] ;# U61.A3 DQU0
|
||||||
|
#set_property -dict {LOC A34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] ;# U61.B8 DQU1
|
||||||
|
#set_property -dict {LOC D34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] ;# U61.C3 DQU2
|
||||||
|
#set_property -dict {LOC A35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] ;# U61.C7 DQU3
|
||||||
|
#set_property -dict {LOC A36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] ;# U61.C2 DQU4
|
||||||
|
#set_property -dict {LOC C35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] ;# U61.C8 DQU5
|
||||||
|
#set_property -dict {LOC B35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] ;# U61.D3 DQU6
|
||||||
|
#set_property -dict {LOC D35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] ;# U61.D7 DQU7
|
||||||
|
#set_property -dict {LOC A39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] ;# U61.G3 DQSL_T
|
||||||
|
#set_property -dict {LOC A40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] ;# U61.F3 DQSL_C
|
||||||
|
#set_property -dict {LOC B36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] ;# U61.B7 DQSU_T
|
||||||
|
#set_property -dict {LOC B37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] ;# U61.A7 DQSU_C
|
||||||
|
#set_property -dict {LOC E39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[2]}] ;# U61.E7 DML_B/DBIL_B
|
||||||
|
#set_property -dict {LOC D37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[3]}] ;# U61.E2 DMU_B/DBIU_B
|
||||||
|
|
||||||
|
#set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] ;# U62.G2 DQL0
|
||||||
|
#set_property -dict {LOC R27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] ;# U62.F7 DQL1
|
||||||
|
#set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] ;# U62.H3 DQL2
|
||||||
|
#set_property -dict {LOC R24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] ;# U62.H7 DQL3
|
||||||
|
#set_property -dict {LOC P24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] ;# U62.H2 DQL4
|
||||||
|
#set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] ;# U62.H8 DQL5
|
||||||
|
#set_property -dict {LOC P27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] ;# U62.J3 DQL6
|
||||||
|
#set_property -dict {LOC T24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] ;# U62.J7 DQL7
|
||||||
|
#set_property -dict {LOC K27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] ;# U62.A3 DQU0
|
||||||
|
#set_property -dict {LOC L26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] ;# U62.B8 DQU1
|
||||||
|
#set_property -dict {LOC J27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] ;# U62.C3 DQU2
|
||||||
|
#set_property -dict {LOC K28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] ;# U62.C7 DQU3
|
||||||
|
#set_property -dict {LOC K26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] ;# U62.C2 DQU4
|
||||||
|
#set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] ;# U62.C8 DQU5
|
||||||
|
#set_property -dict {LOC J26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] ;# U62.D3 DQU6
|
||||||
|
#set_property -dict {LOC L28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] ;# U62.D7 DQU7
|
||||||
|
#set_property -dict {LOC P25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] ;# U62.G3 DQSL_T
|
||||||
|
#set_property -dict {LOC N25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] ;# U62.F3 DQSL_C
|
||||||
|
#set_property -dict {LOC L24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] ;# U62.B7 DQSU_T
|
||||||
|
#set_property -dict {LOC L25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] ;# U62.A7 DQSU_C
|
||||||
|
#set_property -dict {LOC T26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[4]}] ;# U62.E7 DML_B/DBIL_B
|
||||||
|
#set_property -dict {LOC M27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[5]}] ;# U62.E2 DMU_B/DBIU_B
|
||||||
|
|
||||||
|
#set_property -dict {LOC E27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] ;# U63.G2 DQL0
|
||||||
|
#set_property -dict {LOC E28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] ;# U63.F7 DQL1
|
||||||
|
#set_property -dict {LOC E26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] ;# U63.H3 DQL2
|
||||||
|
#set_property -dict {LOC H27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] ;# U63.H7 DQL3
|
||||||
|
#set_property -dict {LOC F25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] ;# U63.H2 DQL4
|
||||||
|
#set_property -dict {LOC F28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] ;# U63.H8 DQL5
|
||||||
|
#set_property -dict {LOC G25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] ;# U63.J3 DQL6
|
||||||
|
#set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] ;# U63.J7 DQL7
|
||||||
|
#set_property -dict {LOC B28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] ;# U63.A3 DQU0
|
||||||
|
#set_property -dict {LOC A28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] ;# U63.B8 DQU1
|
||||||
|
#set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] ;# U63.C3 DQU2
|
||||||
|
#set_property -dict {LOC B27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] ;# U63.C7 DQU3
|
||||||
|
#set_property -dict {LOC D25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] ;# U63.C2 DQU4
|
||||||
|
#set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] ;# U63.C8 DQU5
|
||||||
|
#set_property -dict {LOC C25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] ;# U63.D3 DQU6
|
||||||
|
#set_property -dict {LOC D26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] ;# U63.D7 DQU7
|
||||||
|
#set_property -dict {LOC H28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] ;# U63.G3 DQSL_T
|
||||||
|
#set_property -dict {LOC G28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] ;# U63.F3 DQSL_C
|
||||||
|
#set_property -dict {LOC B26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] ;# U63.B7 DQSU_T
|
||||||
|
#set_property -dict {LOC A26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] ;# U63.A7 DQSU_C
|
||||||
|
#set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[6]}] ;# U63.E7 DML_B/DBIL_B
|
||||||
|
#set_property -dict {LOC D27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[7]}] ;# U63.E2 DMU_B/DBIU_B
|
||||||
|
|
||||||
|
#set_property -dict {LOC N29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] ;# U64.G2 DQL0
|
||||||
|
#set_property -dict {LOC M31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] ;# U64.F7 DQL1
|
||||||
|
#set_property -dict {LOC P29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] ;# U64.H3 DQL2
|
||||||
|
#set_property -dict {LOC L29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] ;# U64.H7 DQL3
|
||||||
|
#set_property -dict {LOC P30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] ;# U64.H2 DQL4
|
||||||
|
#set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] ;# U64.H8 DQL5
|
||||||
|
#set_property -dict {LOC L31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] ;# U64.J3 DQL6
|
||||||
|
#set_property -dict {LOC L30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] ;# U64.J7 DQL7
|
||||||
|
#set_property -dict {LOC H30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[72]}] ;# U64.A3 DQU0
|
||||||
|
#set_property -dict {LOC J32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[73]}] ;# U64.B8 DQU1
|
||||||
|
#set_property -dict {LOC H29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[74]}] ;# U64.C3 DQU2
|
||||||
|
#set_property -dict {LOC H32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[75]}] ;# U64.C7 DQU3
|
||||||
|
#set_property -dict {LOC J29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[76]}] ;# U64.C2 DQU4
|
||||||
|
#set_property -dict {LOC K32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[77]}] ;# U64.C8 DQU5
|
||||||
|
#set_property -dict {LOC J30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[78]}] ;# U64.D3 DQU6
|
||||||
|
#set_property -dict {LOC G32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[79]}] ;# U64.D7 DQU7
|
||||||
|
#set_property -dict {LOC N30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] ;# U64.G3 DQSL_T
|
||||||
|
#set_property -dict {LOC M30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] ;# U64.F3 DQSL_C
|
||||||
|
#set_property -dict {LOC H33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] ;# U64.B7 DQSU_T
|
||||||
|
#set_property -dict {LOC G33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] ;# U64.A7 DQSU_C
|
||||||
|
#set_property -dict {LOC R28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[8]}] ;# U64.E7 DML_B/DBIL_B
|
||||||
|
#set_property -dict {LOC K31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[9]}] ;# U64.E2 DMU_B/DBIU_B
|
||||||
|
|
||||||
|
# DDR4 C2
|
||||||
|
# 5x MT40A256M16GE-075E
|
||||||
|
#set_property -dict {LOC AM27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}]
|
||||||
|
#set_property -dict {LOC AT25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}]
|
||||||
|
#set_property -dict {LOC AN25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}]
|
||||||
|
#set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}]
|
||||||
|
#set_property -dict {LOC AR25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}]
|
||||||
|
#set_property -dict {LOC AU28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}]
|
||||||
|
#set_property -dict {LOC AU27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}]
|
||||||
|
#set_property -dict {LOC AR28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}]
|
||||||
|
#set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}]
|
||||||
|
#set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}]
|
||||||
|
#set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}]
|
||||||
|
#set_property -dict {LOC AN28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}]
|
||||||
|
#set_property -dict {LOC AR27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}]
|
||||||
|
#set_property -dict {LOC AP28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}]
|
||||||
|
#set_property -dict {LOC AL27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}]
|
||||||
|
#set_property -dict {LOC AP27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}]
|
||||||
|
#set_property -dict {LOC AM28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}]
|
||||||
|
#set_property -dict {LOC AU26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}]
|
||||||
|
#set_property -dict {LOC AV26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}]
|
||||||
|
#set_property -dict {LOC AV28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}]
|
||||||
|
#set_property -dict {LOC AT26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t}]
|
||||||
|
#set_property -dict {LOC AT27 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c}]
|
||||||
|
#set_property -dict {LOC AY29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke}]
|
||||||
|
#set_property -dict {LOC AW26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n}]
|
||||||
|
#set_property -dict {LOC AW28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}]
|
||||||
|
#set_property -dict {LOC BB29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt}]
|
||||||
|
#set_property -dict {LOC BF29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}]
|
||||||
|
#set_property -dict {LOC BF40 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}]
|
||||||
|
#set_property -dict {LOC AV25 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_alert_n}]
|
||||||
|
|
||||||
|
#set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] ;# U135.G2 DQL0
|
||||||
|
#set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] ;# U135.F7 DQL1
|
||||||
|
#set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] ;# U135.H3 DQL2
|
||||||
|
#set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] ;# U135.H7 DQL3
|
||||||
|
#set_property -dict {LOC BD31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] ;# U135.H2 DQL4
|
||||||
|
#set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] ;# U135.H8 DQL5
|
||||||
|
#set_property -dict {LOC BD32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] ;# U135.J3 DQL6
|
||||||
|
#set_property -dict {LOC BC31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] ;# U135.J7 DQL7
|
||||||
|
#set_property -dict {LOC BA31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] ;# U135.A3 DQU0
|
||||||
|
#set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] ;# U135.B8 DQU1
|
||||||
|
#set_property -dict {LOC BA30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] ;# U135.C3 DQU2
|
||||||
|
#set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] ;# U135.C7 DQU3
|
||||||
|
#set_property -dict {LOC AW32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] ;# U135.C2 DQU4
|
||||||
|
#set_property -dict {LOC BB33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] ;# U135.C8 DQU5
|
||||||
|
#set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] ;# U135.D3 DQU6
|
||||||
|
#set_property -dict {LOC BA32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] ;# U135.D7 DQU7
|
||||||
|
#set_property -dict {LOC BF30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] ;# U135.G3 DQSL_T
|
||||||
|
#set_property -dict {LOC BF31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] ;# U135.F3 DQSL_C
|
||||||
|
#set_property -dict {LOC AY34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] ;# U135.B7 DQSU_T
|
||||||
|
#set_property -dict {LOC BA34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] ;# U135.A7 DQSU_C
|
||||||
|
#set_property -dict {LOC BE32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[0]}] ;# U135.E7 DML_B/DBIL_B
|
||||||
|
#set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[1]}] ;# U135.E2 DMU_B/DBIU_B
|
||||||
|
|
||||||
|
#set_property -dict {LOC AT31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] ;# U136.G2 DQL0
|
||||||
|
#set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] ;# U136.F7 DQL1
|
||||||
|
#set_property -dict {LOC AV30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] ;# U136.H3 DQL2
|
||||||
|
#set_property -dict {LOC AU33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] ;# U136.H7 DQL3
|
||||||
|
#set_property -dict {LOC AU31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] ;# U136.H2 DQL4
|
||||||
|
#set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] ;# U136.H8 DQL5
|
||||||
|
#set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] ;# U136.J3 DQL6
|
||||||
|
#set_property -dict {LOC AU34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] ;# U136.J7 DQL7
|
||||||
|
#set_property -dict {LOC AT29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] ;# U136.A3 DQU0
|
||||||
|
#set_property -dict {LOC AT34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] ;# U136.B8 DQU1
|
||||||
|
#set_property -dict {LOC AT30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] ;# U136.C3 DQU2
|
||||||
|
#set_property -dict {LOC AR33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] ;# U136.C7 DQU3
|
||||||
|
#set_property -dict {LOC AR30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] ;# U136.C2 DQU4
|
||||||
|
#set_property -dict {LOC AN30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] ;# U136.C8 DQU5
|
||||||
|
#set_property -dict {LOC AP30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] ;# U136.D3 DQU6
|
||||||
|
#set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] ;# U136.D7 DQU7
|
||||||
|
#set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] ;# U136.G3 DQSL_T
|
||||||
|
#set_property -dict {LOC AV29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] ;# U136.F3 DQSL_C
|
||||||
|
#set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] ;# U136.B7 DQSU_T
|
||||||
|
#set_property -dict {LOC AP32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] ;# U136.A7 DQSU_C
|
||||||
|
#set_property -dict {LOC AV33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[2]}] ;# U136.E7 DML_B/DBIL_B
|
||||||
|
#set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[3]}] ;# U136.E2 DMU_B/DBIU_B
|
||||||
|
|
||||||
|
#set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] ;# U137.G2 DQL0
|
||||||
|
#set_property -dict {LOC BF36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] ;# U137.F7 DQL1
|
||||||
|
#set_property -dict {LOC BC35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] ;# U137.H3 DQL2
|
||||||
|
#set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] ;# U137.H7 DQL3
|
||||||
|
#set_property -dict {LOC BE34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] ;# U137.H2 DQL4
|
||||||
|
#set_property -dict {LOC BD36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] ;# U137.H8 DQL5
|
||||||
|
#set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] ;# U137.J3 DQL6
|
||||||
|
#set_property -dict {LOC BC36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] ;# U137.J7 DQL7
|
||||||
|
#set_property -dict {LOC BD37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] ;# U137.A3 DQU0
|
||||||
|
#set_property -dict {LOC BE38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] ;# U137.B8 DQU1
|
||||||
|
#set_property -dict {LOC BD38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] ;# U137.C3 DQU2
|
||||||
|
#set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] ;# U137.C7 DQU3
|
||||||
|
#set_property -dict {LOC BB38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] ;# U137.C2 DQU4
|
||||||
|
#set_property -dict {LOC BB39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] ;# U137.C8 DQU5
|
||||||
|
#set_property -dict {LOC BC39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] ;# U137.D3 DQU6
|
||||||
|
#set_property -dict {LOC BC38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] ;# U137.D7 DQU7
|
||||||
|
#set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] ;# U137.G3 DQSL_T
|
||||||
|
#set_property -dict {LOC BF35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] ;# U137.F3 DQSL_C
|
||||||
|
#set_property -dict {LOC BE39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] ;# U137.B7 DQSU_T
|
||||||
|
#set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] ;# U137.A7 DQSU_C
|
||||||
|
#set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[4]}] ;# U137.E7 DML_B/DBIL_B
|
||||||
|
#set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[5]}] ;# U137.E2 DMU_B/DBIU_B
|
||||||
|
|
||||||
|
#set_property -dict {LOC AW40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] ;# U138.G2 DQL0
|
||||||
|
#set_property -dict {LOC BA40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] ;# U138.F7 DQL1
|
||||||
|
#set_property -dict {LOC AY39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] ;# U138.H3 DQL2
|
||||||
|
#set_property -dict {LOC AY38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] ;# U138.H7 DQL3
|
||||||
|
#set_property -dict {LOC AY40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] ;# U138.H2 DQL4
|
||||||
|
#set_property -dict {LOC BA39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] ;# U138.H8 DQL5
|
||||||
|
#set_property -dict {LOC BB36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] ;# U138.J3 DQL6
|
||||||
|
#set_property -dict {LOC BB37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] ;# U138.J7 DQL7
|
||||||
|
#set_property -dict {LOC AV38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] ;# U138.A3 DQU0
|
||||||
|
#set_property -dict {LOC AU38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] ;# U138.B8 DQU1
|
||||||
|
#set_property -dict {LOC AU39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] ;# U138.C3 DQU2
|
||||||
|
#set_property -dict {LOC AW35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] ;# U138.C7 DQU3
|
||||||
|
#set_property -dict {LOC AU40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] ;# U138.C2 DQU4
|
||||||
|
#set_property -dict {LOC AV40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] ;# U138.C8 DQU5
|
||||||
|
#set_property -dict {LOC AW36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] ;# U138.D3 DQU6
|
||||||
|
#set_property -dict {LOC AV39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] ;# U138.D7 DQU7
|
||||||
|
#set_property -dict {LOC BA35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] ;# U138.G3 DQSL_T
|
||||||
|
#set_property -dict {LOC BA36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] ;# U138.F3 DQSL_C
|
||||||
|
#set_property -dict {LOC AW37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] ;# U138.B7 DQSU_T
|
||||||
|
#set_property -dict {LOC AW38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] ;# U138.A7 DQSU_C
|
||||||
|
#set_property -dict {LOC AY37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[6]}] ;# U138.E7 DML_B/DBIL_B
|
||||||
|
#set_property -dict {LOC AV35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[7]}] ;# U138.E2 DMU_B/DBIU_B
|
||||||
|
|
||||||
|
#set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] ;# U139.G2 DQL0
|
||||||
|
#set_property -dict {LOC BD26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] ;# U139.F7 DQL1
|
||||||
|
#set_property -dict {LOC BD27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] ;# U139.H3 DQL2
|
||||||
|
#set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] ;# U139.H7 DQL3
|
||||||
|
#set_property -dict {LOC BD28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] ;# U139.H2 DQL4
|
||||||
|
#set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] ;# U139.H8 DQL5
|
||||||
|
#set_property -dict {LOC BF26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] ;# U139.J3 DQL6
|
||||||
|
#set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] ;# U139.J7 DQL7
|
||||||
|
#set_property -dict {LOC AY27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[72]}] ;# U139.A3 DQU0
|
||||||
|
#set_property -dict {LOC BC26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[73]}] ;# U139.B8 DQU1
|
||||||
|
#set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[74]}] ;# U139.C3 DQU2
|
||||||
|
#set_property -dict {LOC BB28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[75]}] ;# U139.C7 DQU3
|
||||||
|
#set_property -dict {LOC AY28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[76]}] ;# U139.C2 DQU4
|
||||||
|
#set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[77]}] ;# U139.C8 DQU5
|
||||||
|
#set_property -dict {LOC BC25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[78]}] ;# U139.D3 DQU6
|
||||||
|
#set_property -dict {LOC BC28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[79]}] ;# U139.D7 DQU7
|
||||||
|
#set_property -dict {LOC BE25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] ;# U139.G3 DQSL_T
|
||||||
|
#set_property -dict {LOC BF25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] ;# U139.F3 DQSL_C
|
||||||
|
#set_property -dict {LOC BA26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}] ;# U139.B7 DQSU_T
|
||||||
|
#set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}] ;# U139.A7 DQSU_C
|
||||||
|
#set_property -dict {LOC BE29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[8]}] ;# U139.E7 DML_B/DBIL_B
|
||||||
|
#set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[9]}] ;# U139.E2 DMU_B/DBIU_B
|
||||||
|
|
||||||
|
# BPI flash
|
||||||
|
set_property -dict {LOC AM19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[4]}]
|
||||||
|
set_property -dict {LOC AM18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[5]}]
|
||||||
|
set_property -dict {LOC AN20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[6]}]
|
||||||
|
set_property -dict {LOC AP20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[7]}]
|
||||||
|
set_property -dict {LOC AN19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[8]}]
|
||||||
|
set_property -dict {LOC AN18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[9]}]
|
||||||
|
set_property -dict {LOC AR18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[10]}]
|
||||||
|
set_property -dict {LOC AR17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[11]}]
|
||||||
|
set_property -dict {LOC AT20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[12]}]
|
||||||
|
set_property -dict {LOC AT19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[13]}]
|
||||||
|
set_property -dict {LOC AT17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[14]}]
|
||||||
|
set_property -dict {LOC AU17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[15]}]
|
||||||
|
set_property -dict {LOC AR20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[0]}]
|
||||||
|
set_property -dict {LOC AR19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[1]}]
|
||||||
|
set_property -dict {LOC AV20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[2]}]
|
||||||
|
set_property -dict {LOC AW20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[3]}]
|
||||||
|
set_property -dict {LOC AU19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[4]}]
|
||||||
|
set_property -dict {LOC AU18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[5]}]
|
||||||
|
set_property -dict {LOC AV19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[6]}]
|
||||||
|
set_property -dict {LOC AV18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[7]}]
|
||||||
|
set_property -dict {LOC AW18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[8]}]
|
||||||
|
set_property -dict {LOC AY18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[9]}]
|
||||||
|
set_property -dict {LOC AY19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[10]}]
|
||||||
|
set_property -dict {LOC BA19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[11]}]
|
||||||
|
set_property -dict {LOC BA17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[12]}]
|
||||||
|
set_property -dict {LOC BB17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[13]}]
|
||||||
|
set_property -dict {LOC BB19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[14]}]
|
||||||
|
set_property -dict {LOC BC19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[15]}]
|
||||||
|
set_property -dict {LOC BB18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[16]}]
|
||||||
|
set_property -dict {LOC BC18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[17]}]
|
||||||
|
set_property -dict {LOC AY20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[18]}]
|
||||||
|
set_property -dict {LOC BA20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[19]}]
|
||||||
|
set_property -dict {LOC BD18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[20]}]
|
||||||
|
set_property -dict {LOC BD17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[21]}]
|
||||||
|
set_property -dict {LOC BC20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[22]}]
|
||||||
|
set_property -dict {LOC BD20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[23]}]
|
||||||
|
set_property -dict {LOC BE20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_region[0]}]
|
||||||
|
set_property -dict {LOC BF20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_region[1]}]
|
||||||
|
set_property -dict {LOC BF17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_oe_n}]
|
||||||
|
set_property -dict {LOC BF16 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_we_n}]
|
||||||
|
set_property -dict {LOC AW17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_adv_n}]
|
||||||
|
set_property -dict {LOC BC23 IOSTANDARD LVCMOS18} [get_ports {flash_wait}]
|
||||||
|
|
||||||
|
set_false_path -to [get_ports {flash_dq[*] flash_addr[*] flash_region[*] flash_oe_n flash_we_n flash_adv_n}]
|
||||||
|
set_output_delay 0 [get_ports {flash_dq[*] flash_addr[*] flash_region[*] flash_oe_n flash_we_n flash_adv_n}]
|
||||||
|
set_false_path -from [get_ports {flash_dq[*] flash_wait}]
|
||||||
|
set_input_delay 0 [get_ports {flash_dq[*] flash_wait}]
|
||||||
100
src/cndm/board/VCU108/fpga/fpga/Makefile
Normal file
100
src/cndm/board/VCU108/fpga/fpga/Makefile
Normal file
@@ -0,0 +1,100 @@
|
|||||||
|
# SPDX-License-Identifier: MIT
|
||||||
|
#
|
||||||
|
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||||
|
#
|
||||||
|
# Authors:
|
||||||
|
# - Alex Forencich
|
||||||
|
#
|
||||||
|
|
||||||
|
# FPGA settings
|
||||||
|
FPGA_PART = xcvu095-ffva2104-2-e
|
||||||
|
FPGA_TOP = fpga
|
||||||
|
FPGA_ARCH = virtexu
|
||||||
|
|
||||||
|
RTL_DIR = ../rtl
|
||||||
|
LIB_DIR = ../lib
|
||||||
|
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||||
|
|
||||||
|
# Files for synthesis
|
||||||
|
SYN_FILES = $(RTL_DIR)/fpga.sv
|
||||||
|
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/cndm/rtl/cndm_micro_pcie_us.f
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/pyrite/rtl/pyrite_pcie_us_vsec_bpi.f
|
||||||
|
|
||||||
|
# XDC files
|
||||||
|
XDC_FILES = ../fpga.xdc
|
||||||
|
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||||
|
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||||
|
XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_leaf.tcl
|
||||||
|
XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_phc_regs.tcl
|
||||||
|
XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_rel2tod.tcl
|
||||||
|
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||||
|
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||||
|
|
||||||
|
# IP
|
||||||
|
IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl
|
||||||
|
IP_TCL_FILES += ../ip/pcie3_ultrascale_0.tcl
|
||||||
|
IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_25g_us_gty_25g_156.tcl
|
||||||
|
|
||||||
|
# Configuration
|
||||||
|
CONFIG_TCL_FILES = ./config.tcl
|
||||||
|
|
||||||
|
include ../common/vivado.mk
|
||||||
|
|
||||||
|
program: $(PROJECT).bit
|
||||||
|
echo "open_hw_manager" > program.tcl
|
||||||
|
echo "connect_hw_server" >> program.tcl
|
||||||
|
echo "open_hw_target" >> program.tcl
|
||||||
|
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||||
|
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||||
|
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||||
|
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||||
|
echo "exit" >> program.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||||
|
|
||||||
|
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
|
||||||
|
echo "write_cfgmem -force -format mcs -size 128 -interface BPIx16 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||||
|
echo "exit" >> generate_mcs.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||||
|
mkdir -p rev
|
||||||
|
COUNT=100; \
|
||||||
|
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||||
|
do COUNT=$$((COUNT+1)); done; \
|
||||||
|
COUNT=$$((COUNT-1)); \
|
||||||
|
for x in .mcs .prm; \
|
||||||
|
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||||
|
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||||
|
|
||||||
|
flash: $(PROJECT).mcs $(PROJECT).prm
|
||||||
|
echo "open_hw_manager" > flash.tcl
|
||||||
|
echo "connect_hw_server" >> flash.tcl
|
||||||
|
echo "open_hw_target" >> flash.tcl
|
||||||
|
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||||
|
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||||
|
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt28gu01gaax1e-bpi-x16}] 0]" >> flash.tcl
|
||||||
|
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.BPI_RS_PINS {25:24} [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||||
|
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||||
|
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||||
|
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||||
|
echo "exit" >> flash.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||||
131
src/cndm/board/VCU108/fpga/fpga/config.tcl
Normal file
131
src/cndm/board/VCU108/fpga/fpga/config.tcl
Normal file
@@ -0,0 +1,131 @@
|
|||||||
|
# SPDX-License-Identifier: MIT
|
||||||
|
#
|
||||||
|
# Copyright (c) 2025-2026 FPGA Ninja, LLC
|
||||||
|
#
|
||||||
|
# Authors:
|
||||||
|
# - Alex Forencich
|
||||||
|
#
|
||||||
|
|
||||||
|
set params [dict create]
|
||||||
|
|
||||||
|
# collect build information
|
||||||
|
set build_date [clock seconds]
|
||||||
|
set git_hash 00000000
|
||||||
|
set git_tag ""
|
||||||
|
|
||||||
|
if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } {
|
||||||
|
puts "Error running git or project not under version control"
|
||||||
|
}
|
||||||
|
|
||||||
|
if { [catch {set git_tag [exec git describe --tags HEAD]}] } {
|
||||||
|
puts "Error running git, project not under version control, or no tag found"
|
||||||
|
}
|
||||||
|
|
||||||
|
puts "Build date: ${build_date}"
|
||||||
|
puts "Git hash: ${git_hash}"
|
||||||
|
puts "Git tag: ${git_tag}"
|
||||||
|
|
||||||
|
if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
|
||||||
|
puts "Failed to extract version from git tag"
|
||||||
|
set tag_ver 0.0.1
|
||||||
|
}
|
||||||
|
|
||||||
|
puts "Tag version: ${tag_ver}"
|
||||||
|
|
||||||
|
# FW and board IDs
|
||||||
|
set fpga_id [expr 0x3842093]
|
||||||
|
set fw_id [expr 0x0000C001]
|
||||||
|
set fw_ver $tag_ver
|
||||||
|
set board_vendor_id [expr 0x10ee]
|
||||||
|
set board_device_id [expr 0x806c]
|
||||||
|
set board_ver 1.0
|
||||||
|
set release_info [expr 0x00000000]
|
||||||
|
|
||||||
|
# PCIe IDs
|
||||||
|
set pcie_vendor_id [expr 0x1234]
|
||||||
|
set pcie_device_id [expr 0xC001]
|
||||||
|
set pcie_class_code [expr 0x020000]
|
||||||
|
set pcie_revision_id [expr 0x00]
|
||||||
|
set pcie_subsystem_device_id $board_device_id
|
||||||
|
set pcie_subsystem_vendor_id $board_vendor_id
|
||||||
|
|
||||||
|
# FW ID
|
||||||
|
dict set params FPGA_ID [format "32'h%08x" $fpga_id]
|
||||||
|
dict set params FW_ID [format "32'h%08x" $fw_id]
|
||||||
|
dict set params FW_VER [format "32'h%03x%02x%03x" {*}[split $fw_ver .-] 0 0 0]
|
||||||
|
dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id]
|
||||||
|
dict set params BOARD_VER [format "32'h%03x%02x%03x" {*}[split $board_ver .-] 0 0 0]
|
||||||
|
dict set params BUILD_DATE "32'd${build_date}"
|
||||||
|
dict set params GIT_HASH "32'h${git_hash}"
|
||||||
|
dict set params RELEASE_INFO [format "32'h%08x" $release_info]
|
||||||
|
|
||||||
|
# PTP configuration
|
||||||
|
dict set params PTP_TS_EN "1"
|
||||||
|
|
||||||
|
# AXI lite interface configuration (control)
|
||||||
|
dict set params AXIL_CTRL_DATA_W "32"
|
||||||
|
dict set params AXIL_CTRL_ADDR_W "24"
|
||||||
|
|
||||||
|
# MAC configuration
|
||||||
|
dict set params CFG_LOW_LATENCY "1"
|
||||||
|
dict set params COMBINED_MAC_PCS "1"
|
||||||
|
dict set params MAC_DATA_W "64"
|
||||||
|
|
||||||
|
# PCIe IP core settings
|
||||||
|
set pcie [get_ips pcie3_ultrascale_0]
|
||||||
|
|
||||||
|
# configure BAR settings
|
||||||
|
proc configure_bar {pcie pf bar aperture} {
|
||||||
|
set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes}
|
||||||
|
for { set i 0 } { $i < [llength $size_list] } { incr i } {
|
||||||
|
set scale [lindex $size_list $i]
|
||||||
|
|
||||||
|
if {$aperture > 0 && $aperture < ($i+1)*10} {
|
||||||
|
set size [expr 1 << $aperture - ($i*10)]
|
||||||
|
|
||||||
|
puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)"
|
||||||
|
|
||||||
|
set pcie_config [dict create]
|
||||||
|
|
||||||
|
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_enabled" {true}
|
||||||
|
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_type" {Memory}
|
||||||
|
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_64bit" {true}
|
||||||
|
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_prefetchable" {true}
|
||||||
|
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_scale" $scale
|
||||||
|
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_size" $size
|
||||||
|
|
||||||
|
set_property -dict $pcie_config $pcie
|
||||||
|
|
||||||
|
return
|
||||||
|
}
|
||||||
|
}
|
||||||
|
puts "${pcie} PF${pf} BAR${bar}: disabled"
|
||||||
|
set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie
|
||||||
|
}
|
||||||
|
|
||||||
|
# Control BAR (BAR 0)
|
||||||
|
configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_W]
|
||||||
|
|
||||||
|
# PCIe IP core configuration
|
||||||
|
set pcie_config [dict create]
|
||||||
|
|
||||||
|
# PCIe IDs
|
||||||
|
dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id]
|
||||||
|
dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id]
|
||||||
|
dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code]
|
||||||
|
dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id]
|
||||||
|
dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id]
|
||||||
|
dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id]
|
||||||
|
|
||||||
|
# MSI
|
||||||
|
dict set pcie_config "CONFIG.pf0_msi_enabled" {true}
|
||||||
|
|
||||||
|
set_property -dict $pcie_config $pcie
|
||||||
|
|
||||||
|
# apply parameters to top-level
|
||||||
|
set param_list {}
|
||||||
|
dict for {name value} $params {
|
||||||
|
lappend param_list $name=$value
|
||||||
|
}
|
||||||
|
|
||||||
|
set_property generic $param_list [get_filesets sources_1]
|
||||||
100
src/cndm/board/VCU108/fpga/fpga_10g/Makefile
Normal file
100
src/cndm/board/VCU108/fpga/fpga_10g/Makefile
Normal file
@@ -0,0 +1,100 @@
|
|||||||
|
# SPDX-License-Identifier: MIT
|
||||||
|
#
|
||||||
|
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||||
|
#
|
||||||
|
# Authors:
|
||||||
|
# - Alex Forencich
|
||||||
|
#
|
||||||
|
|
||||||
|
# FPGA settings
|
||||||
|
FPGA_PART = xcvu095-ffva2104-2-e
|
||||||
|
FPGA_TOP = fpga
|
||||||
|
FPGA_ARCH = virtexu
|
||||||
|
|
||||||
|
RTL_DIR = ../rtl
|
||||||
|
LIB_DIR = ../lib
|
||||||
|
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||||
|
|
||||||
|
# Files for synthesis
|
||||||
|
SYN_FILES = $(RTL_DIR)/fpga.sv
|
||||||
|
SYN_FILES += $(RTL_DIR)/fpga_core.sv
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/cndm/rtl/cndm_micro_pcie_us.f
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.f
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||||
|
SYN_FILES += $(TAXI_SRC_DIR)/pyrite/rtl/pyrite_pcie_us_vsec_bpi.f
|
||||||
|
|
||||||
|
# XDC files
|
||||||
|
XDC_FILES = ../fpga.xdc
|
||||||
|
XDC_FILES += $(TAXI_SRC_DIR)/eth/syn/vivado/taxi_eth_mac_fifo.tcl
|
||||||
|
XDC_FILES += $(TAXI_SRC_DIR)/axis/syn/vivado/taxi_axis_async_fifo.tcl
|
||||||
|
XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_leaf.tcl
|
||||||
|
XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_phc_regs.tcl
|
||||||
|
XDC_FILES += $(TAXI_SRC_DIR)/ptp/syn/vivado/taxi_ptp_td_rel2tod.tcl
|
||||||
|
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_reset.tcl
|
||||||
|
XDC_FILES += $(TAXI_SRC_DIR)/sync/syn/vivado/taxi_sync_signal.tcl
|
||||||
|
|
||||||
|
# IP
|
||||||
|
IP_TCL_FILES = ../ip/sgmii_pcs_pma_0.tcl
|
||||||
|
IP_TCL_FILES += ../ip/pcie3_ultrascale_0.tcl
|
||||||
|
IP_TCL_FILES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_phy_10g_us_gty_156.tcl
|
||||||
|
|
||||||
|
# Configuration
|
||||||
|
CONFIG_TCL_FILES = ./config.tcl
|
||||||
|
|
||||||
|
include ../common/vivado.mk
|
||||||
|
|
||||||
|
program: $(PROJECT).bit
|
||||||
|
echo "open_hw_manager" > program.tcl
|
||||||
|
echo "connect_hw_server" >> program.tcl
|
||||||
|
echo "open_hw_target" >> program.tcl
|
||||||
|
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||||
|
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||||
|
echo "set_property PROGRAM.FILE {$(PROJECT).bit} [current_hw_device]" >> program.tcl
|
||||||
|
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||||
|
echo "exit" >> program.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||||
|
|
||||||
|
$(PROJECT).mcs $(PROJECT).prm: $(PROJECT).bit
|
||||||
|
echo "write_cfgmem -force -format mcs -size 128 -interface BPIx16 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||||
|
echo "exit" >> generate_mcs.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||||
|
mkdir -p rev
|
||||||
|
COUNT=100; \
|
||||||
|
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||||
|
do COUNT=$$((COUNT+1)); done; \
|
||||||
|
COUNT=$$((COUNT-1)); \
|
||||||
|
for x in .mcs .prm; \
|
||||||
|
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||||
|
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||||
|
|
||||||
|
flash: $(PROJECT).mcs $(PROJECT).prm
|
||||||
|
echo "open_hw_manager" > flash.tcl
|
||||||
|
echo "connect_hw_server" >> flash.tcl
|
||||||
|
echo "open_hw_target" >> flash.tcl
|
||||||
|
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||||
|
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||||
|
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt28gu01gaax1e-bpi-x16}] 0]" >> flash.tcl
|
||||||
|
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.FILES [list \"$(PROJECT).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.PRM_FILES [list \"$(PROJECT).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.BPI_RS_PINS {25:24} [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||||
|
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||||
|
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||||
|
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||||
|
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||||
|
echo "exit" >> flash.tcl
|
||||||
|
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||||
131
src/cndm/board/VCU108/fpga/fpga_10g/config.tcl
Normal file
131
src/cndm/board/VCU108/fpga/fpga_10g/config.tcl
Normal file
@@ -0,0 +1,131 @@
|
|||||||
|
# SPDX-License-Identifier: MIT
|
||||||
|
#
|
||||||
|
# Copyright (c) 2025-2026 FPGA Ninja, LLC
|
||||||
|
#
|
||||||
|
# Authors:
|
||||||
|
# - Alex Forencich
|
||||||
|
#
|
||||||
|
|
||||||
|
set params [dict create]
|
||||||
|
|
||||||
|
# collect build information
|
||||||
|
set build_date [clock seconds]
|
||||||
|
set git_hash 00000000
|
||||||
|
set git_tag ""
|
||||||
|
|
||||||
|
if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } {
|
||||||
|
puts "Error running git or project not under version control"
|
||||||
|
}
|
||||||
|
|
||||||
|
if { [catch {set git_tag [exec git describe --tags HEAD]}] } {
|
||||||
|
puts "Error running git, project not under version control, or no tag found"
|
||||||
|
}
|
||||||
|
|
||||||
|
puts "Build date: ${build_date}"
|
||||||
|
puts "Git hash: ${git_hash}"
|
||||||
|
puts "Git tag: ${git_tag}"
|
||||||
|
|
||||||
|
if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
|
||||||
|
puts "Failed to extract version from git tag"
|
||||||
|
set tag_ver 0.0.1
|
||||||
|
}
|
||||||
|
|
||||||
|
puts "Tag version: ${tag_ver}"
|
||||||
|
|
||||||
|
# FW and board IDs
|
||||||
|
set fpga_id [expr 0x3842093]
|
||||||
|
set fw_id [expr 0x0000C001]
|
||||||
|
set fw_ver $tag_ver
|
||||||
|
set board_vendor_id [expr 0x10ee]
|
||||||
|
set board_device_id [expr 0x806c]
|
||||||
|
set board_ver 1.0
|
||||||
|
set release_info [expr 0x00000000]
|
||||||
|
|
||||||
|
# PCIe IDs
|
||||||
|
set pcie_vendor_id [expr 0x1234]
|
||||||
|
set pcie_device_id [expr 0xC001]
|
||||||
|
set pcie_class_code [expr 0x020000]
|
||||||
|
set pcie_revision_id [expr 0x00]
|
||||||
|
set pcie_subsystem_device_id $board_device_id
|
||||||
|
set pcie_subsystem_vendor_id $board_vendor_id
|
||||||
|
|
||||||
|
# FW ID
|
||||||
|
dict set params FPGA_ID [format "32'h%08x" $fpga_id]
|
||||||
|
dict set params FW_ID [format "32'h%08x" $fw_id]
|
||||||
|
dict set params FW_VER [format "32'h%03x%02x%03x" {*}[split $fw_ver .-] 0 0 0]
|
||||||
|
dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id]
|
||||||
|
dict set params BOARD_VER [format "32'h%03x%02x%03x" {*}[split $board_ver .-] 0 0 0]
|
||||||
|
dict set params BUILD_DATE "32'd${build_date}"
|
||||||
|
dict set params GIT_HASH "32'h${git_hash}"
|
||||||
|
dict set params RELEASE_INFO [format "32'h%08x" $release_info]
|
||||||
|
|
||||||
|
# PTP configuration
|
||||||
|
dict set params PTP_TS_EN "1"
|
||||||
|
|
||||||
|
# AXI lite interface configuration (control)
|
||||||
|
dict set params AXIL_CTRL_DATA_W "32"
|
||||||
|
dict set params AXIL_CTRL_ADDR_W "24"
|
||||||
|
|
||||||
|
# MAC configuration
|
||||||
|
dict set params CFG_LOW_LATENCY "1"
|
||||||
|
dict set params COMBINED_MAC_PCS "1"
|
||||||
|
dict set params MAC_DATA_W "32"
|
||||||
|
|
||||||
|
# PCIe IP core settings
|
||||||
|
set pcie [get_ips pcie3_ultrascale_0]
|
||||||
|
|
||||||
|
# configure BAR settings
|
||||||
|
proc configure_bar {pcie pf bar aperture} {
|
||||||
|
set size_list {Bytes Kilobytes Megabytes Gigabytes Terabytes Petabytes Exabytes}
|
||||||
|
for { set i 0 } { $i < [llength $size_list] } { incr i } {
|
||||||
|
set scale [lindex $size_list $i]
|
||||||
|
|
||||||
|
if {$aperture > 0 && $aperture < ($i+1)*10} {
|
||||||
|
set size [expr 1 << $aperture - ($i*10)]
|
||||||
|
|
||||||
|
puts "${pcie} PF${pf} BAR${bar}: aperture ${aperture} bits ($size $scale)"
|
||||||
|
|
||||||
|
set pcie_config [dict create]
|
||||||
|
|
||||||
|
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_enabled" {true}
|
||||||
|
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_type" {Memory}
|
||||||
|
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_64bit" {true}
|
||||||
|
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_prefetchable" {true}
|
||||||
|
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_scale" $scale
|
||||||
|
dict set pcie_config "CONFIG.pf${pf}_bar${bar}_size" $size
|
||||||
|
|
||||||
|
set_property -dict $pcie_config $pcie
|
||||||
|
|
||||||
|
return
|
||||||
|
}
|
||||||
|
}
|
||||||
|
puts "${pcie} PF${pf} BAR${bar}: disabled"
|
||||||
|
set_property "CONFIG.pf${pf}_bar${bar}_enabled" {false} $pcie
|
||||||
|
}
|
||||||
|
|
||||||
|
# Control BAR (BAR 0)
|
||||||
|
configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_W]
|
||||||
|
|
||||||
|
# PCIe IP core configuration
|
||||||
|
set pcie_config [dict create]
|
||||||
|
|
||||||
|
# PCIe IDs
|
||||||
|
dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id]
|
||||||
|
dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id]
|
||||||
|
dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code]
|
||||||
|
dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id]
|
||||||
|
dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id]
|
||||||
|
dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id]
|
||||||
|
|
||||||
|
# MSI
|
||||||
|
dict set pcie_config "CONFIG.pf0_msi_enabled" {true}
|
||||||
|
|
||||||
|
set_property -dict $pcie_config $pcie
|
||||||
|
|
||||||
|
# apply parameters to top-level
|
||||||
|
set param_list {}
|
||||||
|
dict for {name value} $params {
|
||||||
|
lappend param_list $name=$value
|
||||||
|
}
|
||||||
|
|
||||||
|
set_property generic $param_list [get_filesets sources_1]
|
||||||
29
src/cndm/board/VCU108/fpga/ip/pcie3_ultrascale_0.tcl
Normal file
29
src/cndm/board/VCU108/fpga/ip/pcie3_ultrascale_0.tcl
Normal file
@@ -0,0 +1,29 @@
|
|||||||
|
|
||||||
|
create_ip -name pcie3_ultrascale -vendor xilinx.com -library ip -module_name pcie3_ultrascale_0
|
||||||
|
|
||||||
|
set_property -dict [list \
|
||||||
|
CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
|
||||||
|
CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \
|
||||||
|
CONFIG.AXISTEN_IF_RC_STRADDLE {false} \
|
||||||
|
CONFIG.axisten_if_width {256_bit} \
|
||||||
|
CONFIG.extended_tag_field {true} \
|
||||||
|
CONFIG.pf0_dev_cap_max_payload {1024_bytes} \
|
||||||
|
CONFIG.axisten_freq {250} \
|
||||||
|
CONFIG.PF0_Use_Class_Code_Lookup_Assistant {false} \
|
||||||
|
CONFIG.pf0_class_code_base {02} \
|
||||||
|
CONFIG.pf0_class_code_sub {00} \
|
||||||
|
CONFIG.pf0_class_code_interface {00} \
|
||||||
|
CONFIG.PF0_DEVICE_ID {C001} \
|
||||||
|
CONFIG.PF0_SUBSYSTEM_ID {806c} \
|
||||||
|
CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \
|
||||||
|
CONFIG.pf0_bar0_64bit {true} \
|
||||||
|
CONFIG.pf0_bar0_prefetchable {true} \
|
||||||
|
CONFIG.pf0_bar0_scale {Megabytes} \
|
||||||
|
CONFIG.pf0_bar0_size {16} \
|
||||||
|
CONFIG.pf0_msi_enabled {true} \
|
||||||
|
CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \
|
||||||
|
CONFIG.en_msi_per_vec_masking {true} \
|
||||||
|
CONFIG.ext_pcie_cfg_space_enabled {true} \
|
||||||
|
CONFIG.vendor_id {1234} \
|
||||||
|
CONFIG.mode_selection {Advanced} \
|
||||||
|
] [get_ips pcie3_ultrascale_0]
|
||||||
17
src/cndm/board/VCU108/fpga/ip/sgmii_pcs_pma_0.tcl
Normal file
17
src/cndm/board/VCU108/fpga/ip/sgmii_pcs_pma_0.tcl
Normal file
@@ -0,0 +1,17 @@
|
|||||||
|
# SPDX-License-Identifier: MIT
|
||||||
|
#
|
||||||
|
# Copyright (c) 2025 FPGA Ninja, LLC
|
||||||
|
#
|
||||||
|
# Authors:
|
||||||
|
# - Alex Forencich
|
||||||
|
#
|
||||||
|
|
||||||
|
create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name sgmii_pcs_pma_0
|
||||||
|
|
||||||
|
set_property -dict [list \
|
||||||
|
CONFIG.Standard {SGMII} \
|
||||||
|
CONFIG.Physical_Interface {LVDS} \
|
||||||
|
CONFIG.Management_Interface {false} \
|
||||||
|
CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \
|
||||||
|
CONFIG.LvdsRefClk {625} \
|
||||||
|
] [get_ips sgmii_pcs_pma_0]
|
||||||
1
src/cndm/board/VCU108/fpga/lib/taxi
Symbolic link
1
src/cndm/board/VCU108/fpga/lib/taxi
Symbolic link
@@ -0,0 +1 @@
|
|||||||
|
../../../../../../
|
||||||
1088
src/cndm/board/VCU108/fpga/rtl/fpga.sv
Normal file
1088
src/cndm/board/VCU108/fpga/rtl/fpga.sv
Normal file
File diff suppressed because it is too large
Load Diff
914
src/cndm/board/VCU108/fpga/rtl/fpga_core.sv
Normal file
914
src/cndm/board/VCU108/fpga/rtl/fpga_core.sv
Normal file
@@ -0,0 +1,914 @@
|
|||||||
|
// SPDX-License-Identifier: MIT
|
||||||
|
/*
|
||||||
|
|
||||||
|
Copyright (c) 2014-2026 FPGA Ninja, LLC
|
||||||
|
|
||||||
|
Authors:
|
||||||
|
- Alex Forencich
|
||||||
|
|
||||||
|
*/
|
||||||
|
|
||||||
|
`resetall
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
`default_nettype none
|
||||||
|
|
||||||
|
/*
|
||||||
|
* FPGA core logic
|
||||||
|
*/
|
||||||
|
module fpga_core #
|
||||||
|
(
|
||||||
|
// simulation (set to avoid vendor primitives)
|
||||||
|
parameter logic SIM = 1'b0,
|
||||||
|
// vendor ("GENERIC", "XILINX", "ALTERA")
|
||||||
|
parameter string VENDOR = "XILINX",
|
||||||
|
// device family
|
||||||
|
parameter string FAMILY = "virtexu",
|
||||||
|
|
||||||
|
// FW ID
|
||||||
|
parameter FPGA_ID = 32'h3842093,
|
||||||
|
parameter FW_ID = 32'h0000C001,
|
||||||
|
parameter FW_VER = 32'h000_01_000,
|
||||||
|
parameter BOARD_ID = 32'h10ee_806c,
|
||||||
|
parameter BOARD_VER = 32'h001_00_000,
|
||||||
|
parameter BUILD_DATE = 32'd602976000,
|
||||||
|
parameter GIT_HASH = 32'h5f87c2e8,
|
||||||
|
parameter RELEASE_INFO = 32'h00000000,
|
||||||
|
|
||||||
|
// PTP configuration
|
||||||
|
parameter logic PTP_TS_EN = 1'b1,
|
||||||
|
|
||||||
|
// PCIe interface configuration
|
||||||
|
parameter RQ_SEQ_NUM_W = 6,
|
||||||
|
|
||||||
|
// AXI lite interface configuration (control)
|
||||||
|
parameter AXIL_CTRL_DATA_W = 32,
|
||||||
|
parameter AXIL_CTRL_ADDR_W = 24,
|
||||||
|
|
||||||
|
// MAC configuration
|
||||||
|
parameter logic CFG_LOW_LATENCY = 1'b1,
|
||||||
|
parameter logic COMBINED_MAC_PCS = 1'b1,
|
||||||
|
parameter MAC_DATA_W = 64
|
||||||
|
)
|
||||||
|
(
|
||||||
|
/*
|
||||||
|
* Clock: 125MHz
|
||||||
|
* Synchronous reset
|
||||||
|
*/
|
||||||
|
input wire logic clk_125mhz,
|
||||||
|
input wire logic rst_125mhz,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* GPIO
|
||||||
|
*/
|
||||||
|
input wire logic btnu,
|
||||||
|
input wire logic btnl,
|
||||||
|
input wire logic btnd,
|
||||||
|
input wire logic btnr,
|
||||||
|
input wire logic btnc,
|
||||||
|
input wire logic [3:0] sw,
|
||||||
|
output wire logic [7:0] led,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* UART: 115200 bps, 8N1
|
||||||
|
*/
|
||||||
|
input wire logic uart_rxd,
|
||||||
|
output wire logic uart_txd,
|
||||||
|
input wire logic uart_rts,
|
||||||
|
output wire logic uart_cts,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Ethernet: 1000BASE-T SGMII
|
||||||
|
*/
|
||||||
|
input wire logic phy_gmii_clk,
|
||||||
|
input wire logic phy_gmii_rst,
|
||||||
|
input wire logic phy_gmii_clk_en,
|
||||||
|
input wire logic [7:0] phy_gmii_rxd,
|
||||||
|
input wire logic phy_gmii_rx_dv,
|
||||||
|
input wire logic phy_gmii_rx_er,
|
||||||
|
output wire logic [7:0] phy_gmii_txd,
|
||||||
|
output wire logic phy_gmii_tx_en,
|
||||||
|
output wire logic phy_gmii_tx_er,
|
||||||
|
output wire logic phy_reset_n,
|
||||||
|
input wire logic phy_int_n,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Ethernet: QSFP28
|
||||||
|
*/
|
||||||
|
input wire logic qsfp_rx_p[4],
|
||||||
|
input wire logic qsfp_rx_n[4],
|
||||||
|
output wire logic qsfp_tx_p[4],
|
||||||
|
output wire logic qsfp_tx_n[4],
|
||||||
|
input wire logic qsfp_mgt_refclk_0_p,
|
||||||
|
input wire logic qsfp_mgt_refclk_0_n,
|
||||||
|
// input wire logic qsfp_mgt_refclk_1_p,
|
||||||
|
// input wire logic qsfp_mgt_refclk_1_n,
|
||||||
|
// output wire logic qsfp_recclk_p,
|
||||||
|
// output wire logic qsfp_recclk_n,
|
||||||
|
output wire logic qsfp_modsell,
|
||||||
|
output wire logic qsfp_resetl,
|
||||||
|
input wire logic qsfp_modprsl,
|
||||||
|
input wire logic qsfp_intl,
|
||||||
|
output wire logic qsfp_lpmode,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* PCIe
|
||||||
|
*/
|
||||||
|
input wire logic pcie_clk,
|
||||||
|
input wire logic pcie_rst,
|
||||||
|
taxi_axis_if.snk s_axis_pcie_cq,
|
||||||
|
taxi_axis_if.src m_axis_pcie_cc,
|
||||||
|
taxi_axis_if.src m_axis_pcie_rq,
|
||||||
|
taxi_axis_if.snk s_axis_pcie_rc,
|
||||||
|
|
||||||
|
input wire logic [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num,
|
||||||
|
input wire logic pcie_rq_seq_num_vld,
|
||||||
|
|
||||||
|
input wire logic [2:0] cfg_max_payload,
|
||||||
|
input wire logic [2:0] cfg_max_read_req,
|
||||||
|
input wire logic [3:0] cfg_rcb_status,
|
||||||
|
|
||||||
|
output wire logic [18:0] cfg_mgmt_addr,
|
||||||
|
output wire logic cfg_mgmt_write,
|
||||||
|
output wire logic [31:0] cfg_mgmt_write_data,
|
||||||
|
output wire logic [3:0] cfg_mgmt_byte_enable,
|
||||||
|
output wire logic cfg_mgmt_read,
|
||||||
|
output wire logic [31:0] cfg_mgmt_read_data,
|
||||||
|
input wire logic cfg_mgmt_read_write_done,
|
||||||
|
|
||||||
|
input wire logic [7:0] cfg_fc_ph,
|
||||||
|
input wire logic [11:0] cfg_fc_pd,
|
||||||
|
input wire logic [7:0] cfg_fc_nph,
|
||||||
|
input wire logic [11:0] cfg_fc_npd,
|
||||||
|
input wire logic [7:0] cfg_fc_cplh,
|
||||||
|
input wire logic [11:0] cfg_fc_cpld,
|
||||||
|
output wire logic [2:0] cfg_fc_sel,
|
||||||
|
|
||||||
|
input wire logic cfg_ext_read_received,
|
||||||
|
input wire logic cfg_ext_write_received,
|
||||||
|
input wire logic [9:0] cfg_ext_register_number,
|
||||||
|
input wire logic [7:0] cfg_ext_function_number,
|
||||||
|
input wire logic [31:0] cfg_ext_write_data,
|
||||||
|
input wire logic [3:0] cfg_ext_write_byte_enable,
|
||||||
|
output wire logic [31:0] cfg_ext_read_data,
|
||||||
|
output wire logic cfg_ext_read_data_valid,
|
||||||
|
|
||||||
|
input wire logic [3:0] cfg_interrupt_msi_enable,
|
||||||
|
input wire logic [11:0] cfg_interrupt_msi_mmenable,
|
||||||
|
input wire logic cfg_interrupt_msi_mask_update,
|
||||||
|
input wire logic [31:0] cfg_interrupt_msi_data,
|
||||||
|
output wire logic [3:0] cfg_interrupt_msi_select,
|
||||||
|
output wire logic [31:0] cfg_interrupt_msi_int,
|
||||||
|
output wire logic [31:0] cfg_interrupt_msi_pending_status,
|
||||||
|
output wire logic cfg_interrupt_msi_pending_status_data_enable,
|
||||||
|
output wire logic [3:0] cfg_interrupt_msi_pending_status_function_num,
|
||||||
|
input wire logic cfg_interrupt_msi_sent,
|
||||||
|
input wire logic cfg_interrupt_msi_fail,
|
||||||
|
output wire logic [2:0] cfg_interrupt_msi_attr,
|
||||||
|
output wire logic cfg_interrupt_msi_tph_present,
|
||||||
|
output wire logic [1:0] cfg_interrupt_msi_tph_type,
|
||||||
|
output wire logic [8:0] cfg_interrupt_msi_tph_st_tag,
|
||||||
|
output wire logic [3:0] cfg_interrupt_msi_function_number,
|
||||||
|
|
||||||
|
/*
|
||||||
|
* BPI flash
|
||||||
|
*/
|
||||||
|
output wire logic fpga_boot,
|
||||||
|
input wire logic [15:0] flash_dq_i,
|
||||||
|
output wire logic [15:0] flash_dq_o,
|
||||||
|
output wire logic flash_dq_oe,
|
||||||
|
output wire logic [23:0] flash_addr,
|
||||||
|
output wire logic [1:0] flash_region,
|
||||||
|
output wire logic flash_region_oe,
|
||||||
|
output wire logic flash_ce_n,
|
||||||
|
output wire logic flash_oe_n,
|
||||||
|
output wire logic flash_we_n,
|
||||||
|
output wire logic flash_adv_n
|
||||||
|
);
|
||||||
|
|
||||||
|
localparam logic PTP_TS_FMT_TOD = 1'b0;
|
||||||
|
localparam PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 48;
|
||||||
|
|
||||||
|
// flashing via PCIe VSEC
|
||||||
|
pyrite_pcie_us_vsec_bpi #(
|
||||||
|
.EXT_CAP_ID(16'h000B),
|
||||||
|
.EXT_CAP_VERSION(4'h1),
|
||||||
|
.EXT_CAP_OFFSET(12'h480),
|
||||||
|
.EXT_CAP_NEXT(12'h000),
|
||||||
|
.EXT_CAP_VSEC_ID(16'h00DB),
|
||||||
|
.EXT_CAP_VSEC_REV(4'h1),
|
||||||
|
|
||||||
|
// FW ID
|
||||||
|
.FPGA_ID(FPGA_ID),
|
||||||
|
.FW_ID(FW_ID),
|
||||||
|
.FW_VER(FW_VER),
|
||||||
|
.BOARD_ID(BOARD_ID),
|
||||||
|
.BOARD_VER(BOARD_VER),
|
||||||
|
.BUILD_DATE(BUILD_DATE),
|
||||||
|
.GIT_HASH(GIT_HASH),
|
||||||
|
.RELEASE_INFO(RELEASE_INFO),
|
||||||
|
|
||||||
|
// Flash
|
||||||
|
.FLASH_SEG_COUNT(4),
|
||||||
|
.FLASH_SEG_DEFAULT(1),
|
||||||
|
.FLASH_SEG_FALLBACK(0),
|
||||||
|
.FLASH_SEG0_SIZE(32'h00000000),
|
||||||
|
.FLASH_DATA_W(16),
|
||||||
|
.FLASH_ADDR_W(24),
|
||||||
|
.FLASH_RGN_W(2)
|
||||||
|
)
|
||||||
|
pyrite_inst (
|
||||||
|
.clk(pcie_clk),
|
||||||
|
.rst(pcie_rst),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* PCIe
|
||||||
|
*/
|
||||||
|
.cfg_ext_read_received(cfg_ext_read_received),
|
||||||
|
.cfg_ext_write_received(cfg_ext_write_received),
|
||||||
|
.cfg_ext_register_number(cfg_ext_register_number),
|
||||||
|
.cfg_ext_function_number(cfg_ext_function_number),
|
||||||
|
.cfg_ext_write_data(cfg_ext_write_data),
|
||||||
|
.cfg_ext_write_byte_enable(cfg_ext_write_byte_enable),
|
||||||
|
.cfg_ext_read_data(cfg_ext_read_data),
|
||||||
|
.cfg_ext_read_data_valid(cfg_ext_read_data_valid),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* BPI flash
|
||||||
|
*/
|
||||||
|
.fpga_boot(fpga_boot),
|
||||||
|
.flash_dq_i(flash_dq_i),
|
||||||
|
.flash_dq_o(flash_dq_o),
|
||||||
|
.flash_dq_oe(flash_dq_oe),
|
||||||
|
.flash_addr(flash_addr),
|
||||||
|
.flash_region(flash_region),
|
||||||
|
.flash_region_oe(flash_region_oe),
|
||||||
|
.flash_ce_n(flash_ce_n),
|
||||||
|
.flash_oe_n(flash_oe_n),
|
||||||
|
.flash_we_n(flash_we_n),
|
||||||
|
.flash_adv_n(flash_adv_n)
|
||||||
|
);
|
||||||
|
|
||||||
|
// XFCP
|
||||||
|
assign uart_cts = 1'b0;
|
||||||
|
|
||||||
|
taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_ds(), xfcp_us();
|
||||||
|
|
||||||
|
taxi_xfcp_if_uart #(
|
||||||
|
.TX_FIFO_DEPTH(512),
|
||||||
|
.RX_FIFO_DEPTH(512)
|
||||||
|
)
|
||||||
|
xfcp_if_uart_inst (
|
||||||
|
.clk(clk_125mhz),
|
||||||
|
.rst(rst_125mhz),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* UART interface
|
||||||
|
*/
|
||||||
|
.uart_rxd(uart_rxd),
|
||||||
|
.uart_txd(uart_txd),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* XFCP downstream interface
|
||||||
|
*/
|
||||||
|
.xfcp_dsp_ds(xfcp_ds),
|
||||||
|
.xfcp_dsp_us(xfcp_us),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Configuration
|
||||||
|
*/
|
||||||
|
.prescale(16'(125000000/921600))
|
||||||
|
);
|
||||||
|
|
||||||
|
localparam XFCP_PORTS = 2;
|
||||||
|
|
||||||
|
taxi_axis_if #(.DATA_W(8), .USER_EN(1), .USER_W(1)) xfcp_sw_ds[XFCP_PORTS](), xfcp_sw_us[XFCP_PORTS]();
|
||||||
|
|
||||||
|
taxi_xfcp_switch #(
|
||||||
|
.XFCP_ID_STR("VCU108"),
|
||||||
|
.XFCP_EXT_ID(0),
|
||||||
|
.XFCP_EXT_ID_STR("Taxi example"),
|
||||||
|
.PORTS($size(xfcp_sw_us))
|
||||||
|
)
|
||||||
|
xfcp_sw_inst (
|
||||||
|
.clk(clk_125mhz),
|
||||||
|
.rst(rst_125mhz),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* XFCP upstream port
|
||||||
|
*/
|
||||||
|
.xfcp_usp_ds(xfcp_ds),
|
||||||
|
.xfcp_usp_us(xfcp_us),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* XFCP downstream ports
|
||||||
|
*/
|
||||||
|
.xfcp_dsp_ds(xfcp_sw_ds),
|
||||||
|
.xfcp_dsp_us(xfcp_sw_us)
|
||||||
|
);
|
||||||
|
|
||||||
|
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_stat();
|
||||||
|
|
||||||
|
taxi_xfcp_mod_stats #(
|
||||||
|
.XFCP_ID_STR("Statistics"),
|
||||||
|
.XFCP_EXT_ID(0),
|
||||||
|
.XFCP_EXT_ID_STR(""),
|
||||||
|
.STAT_COUNT_W(64),
|
||||||
|
.STAT_PIPELINE(2)
|
||||||
|
)
|
||||||
|
xfcp_stats_inst (
|
||||||
|
.clk(clk_125mhz),
|
||||||
|
.rst(rst_125mhz),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* XFCP upstream port
|
||||||
|
*/
|
||||||
|
.xfcp_usp_ds(xfcp_sw_ds[0]),
|
||||||
|
.xfcp_usp_us(xfcp_sw_us[0]),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Statistics increment input
|
||||||
|
*/
|
||||||
|
.s_axis_stat(axis_stat)
|
||||||
|
);
|
||||||
|
|
||||||
|
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(10)) axis_eth_stat[2]();
|
||||||
|
|
||||||
|
taxi_axis_arb_mux #(
|
||||||
|
.S_COUNT($size(axis_eth_stat)),
|
||||||
|
.UPDATE_TID(1'b0),
|
||||||
|
.ARB_ROUND_ROBIN(1'b1),
|
||||||
|
.ARB_LSB_HIGH_PRIO(1'b0)
|
||||||
|
)
|
||||||
|
stat_mux_inst (
|
||||||
|
.clk(clk_125mhz),
|
||||||
|
.rst(rst_125mhz),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* AXI4-Stream inputs (sink)
|
||||||
|
*/
|
||||||
|
.s_axis(axis_eth_stat),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* AXI4-Stream output (source)
|
||||||
|
*/
|
||||||
|
.m_axis(axis_stat)
|
||||||
|
);
|
||||||
|
|
||||||
|
// BASE-T PHY
|
||||||
|
assign phy_reset_n = !rst_125mhz;
|
||||||
|
|
||||||
|
taxi_axis_if #(.DATA_W(8), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_eth();
|
||||||
|
taxi_axis_if #(.DATA_W(96), .KEEP_W(1), .ID_W(8)) axis_tx_cpl();
|
||||||
|
|
||||||
|
taxi_eth_mac_1g_fifo #(
|
||||||
|
.PADDING_EN(1),
|
||||||
|
.MIN_FRAME_LEN(64),
|
||||||
|
.STAT_EN(1),
|
||||||
|
.STAT_TX_LEVEL(1),
|
||||||
|
.STAT_RX_LEVEL(1),
|
||||||
|
.STAT_ID_BASE(0),
|
||||||
|
.STAT_UPDATE_PERIOD(1024),
|
||||||
|
.STAT_STR_EN(1),
|
||||||
|
.STAT_PREFIX_STR("SGMII0"),
|
||||||
|
.TX_FIFO_DEPTH(16384),
|
||||||
|
.TX_FRAME_FIFO(1),
|
||||||
|
.RX_FIFO_DEPTH(16384),
|
||||||
|
.RX_FRAME_FIFO(1)
|
||||||
|
)
|
||||||
|
eth_mac_inst (
|
||||||
|
.rx_clk(phy_gmii_clk),
|
||||||
|
.rx_rst(phy_gmii_rst),
|
||||||
|
.tx_clk(phy_gmii_clk),
|
||||||
|
.tx_rst(phy_gmii_rst),
|
||||||
|
.logic_clk(clk_125mhz),
|
||||||
|
.logic_rst(rst_125mhz),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Transmit interface (AXI stream)
|
||||||
|
*/
|
||||||
|
.s_axis_tx(axis_eth),
|
||||||
|
.m_axis_tx_cpl(axis_tx_cpl),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Receive interface (AXI stream)
|
||||||
|
*/
|
||||||
|
.m_axis_rx(axis_eth),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* GMII interface
|
||||||
|
*/
|
||||||
|
.gmii_rxd(phy_gmii_rxd),
|
||||||
|
.gmii_rx_dv(phy_gmii_rx_dv),
|
||||||
|
.gmii_rx_er(phy_gmii_rx_er),
|
||||||
|
.gmii_txd(phy_gmii_txd),
|
||||||
|
.gmii_tx_en(phy_gmii_tx_en),
|
||||||
|
.gmii_tx_er(phy_gmii_tx_er),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Control
|
||||||
|
*/
|
||||||
|
.rx_clk_enable(phy_gmii_clk_en),
|
||||||
|
.tx_clk_enable(phy_gmii_clk_en),
|
||||||
|
.rx_mii_select(1'b0),
|
||||||
|
.tx_mii_select(1'b0),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Statistics
|
||||||
|
*/
|
||||||
|
.stat_clk(clk_125mhz),
|
||||||
|
.stat_rst(rst_125mhz),
|
||||||
|
.m_axis_stat(axis_eth_stat[0]),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Status
|
||||||
|
*/
|
||||||
|
.tx_error_underflow(),
|
||||||
|
.tx_fifo_overflow(),
|
||||||
|
.tx_fifo_bad_frame(),
|
||||||
|
.tx_fifo_good_frame(),
|
||||||
|
.rx_error_bad_frame(),
|
||||||
|
.rx_error_bad_fcs(),
|
||||||
|
.rx_fifo_overflow(),
|
||||||
|
.rx_fifo_bad_frame(),
|
||||||
|
.rx_fifo_good_frame(),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Configuration
|
||||||
|
*/
|
||||||
|
.cfg_tx_max_pkt_len(16'd9218),
|
||||||
|
.cfg_tx_ifg(8'd12),
|
||||||
|
.cfg_tx_enable(1'b1),
|
||||||
|
.cfg_rx_max_pkt_len(16'd9218),
|
||||||
|
.cfg_rx_enable(1'b1)
|
||||||
|
);
|
||||||
|
|
||||||
|
// QSFP28
|
||||||
|
assign qsfp_modsell = 1'b0;
|
||||||
|
assign qsfp_resetl = 1'b1;
|
||||||
|
assign qsfp_lpmode = 1'b0;
|
||||||
|
|
||||||
|
wire qsfp_tx_clk[4];
|
||||||
|
wire qsfp_tx_rst[4];
|
||||||
|
wire qsfp_rx_clk[4];
|
||||||
|
wire qsfp_rx_rst[4];
|
||||||
|
|
||||||
|
wire qsfp_rx_status[4];
|
||||||
|
|
||||||
|
assign led[0] = qsfp_rx_status[0];
|
||||||
|
assign led[1] = qsfp_rx_status[1];
|
||||||
|
assign led[2] = qsfp_rx_status[2];
|
||||||
|
assign led[3] = qsfp_rx_status[3];
|
||||||
|
assign led[4] = 1'b0;
|
||||||
|
assign led[5] = 1'b0;
|
||||||
|
assign led[6] = 1'b0;
|
||||||
|
// assign led[7] = 1'b0;
|
||||||
|
|
||||||
|
wire qsfp_gtpowergood;
|
||||||
|
|
||||||
|
wire qsfp_mgt_refclk_0;
|
||||||
|
wire qsfp_mgt_refclk_0_int;
|
||||||
|
wire qsfp_mgt_refclk_0_bufg;
|
||||||
|
|
||||||
|
wire qsfp_rst;
|
||||||
|
|
||||||
|
taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1)) axis_qsfp_tx[4]();
|
||||||
|
taxi_axis_if #(.DATA_W(PTP_TS_W), .KEEP_W(1), .ID_W(8)) axis_qsfp_tx_cpl[4]();
|
||||||
|
taxi_axis_if #(.DATA_W(MAC_DATA_W), .ID_W(8), .USER_EN(1), .USER_W(1+PTP_TS_W)) axis_qsfp_rx[4]();
|
||||||
|
taxi_axis_if #(.DATA_W(16), .KEEP_W(1), .KEEP_EN(0), .LAST_EN(0), .USER_EN(1), .USER_W(1), .ID_EN(1), .ID_W(8)) axis_qsfp_stat();
|
||||||
|
|
||||||
|
if (SIM) begin
|
||||||
|
|
||||||
|
assign qsfp_mgt_refclk_0 = qsfp_mgt_refclk_0_p;
|
||||||
|
assign qsfp_mgt_refclk_0_int = qsfp_mgt_refclk_0_p;
|
||||||
|
assign qsfp_mgt_refclk_0_bufg = qsfp_mgt_refclk_0_int;
|
||||||
|
|
||||||
|
end else begin
|
||||||
|
|
||||||
|
IBUFDS_GTE3 ibufds_gte3_qsfp_mgt_refclk_0_inst (
|
||||||
|
.I (qsfp_mgt_refclk_0_p),
|
||||||
|
.IB (qsfp_mgt_refclk_0_n),
|
||||||
|
.CEB (1'b0),
|
||||||
|
.O (qsfp_mgt_refclk_0),
|
||||||
|
.ODIV2 (qsfp_mgt_refclk_0_int)
|
||||||
|
);
|
||||||
|
|
||||||
|
BUFG_GT bufg_gt_qsfp_mgt_refclk_0_inst (
|
||||||
|
.CE (qsfp_gtpowergood),
|
||||||
|
.CEMASK (1'b1),
|
||||||
|
.CLR (1'b0),
|
||||||
|
.CLRMASK (1'b1),
|
||||||
|
.DIV (3'd0),
|
||||||
|
.I (qsfp_mgt_refclk_0_int),
|
||||||
|
.O (qsfp_mgt_refclk_0_bufg)
|
||||||
|
);
|
||||||
|
|
||||||
|
end
|
||||||
|
|
||||||
|
taxi_sync_reset #(
|
||||||
|
.N(4)
|
||||||
|
)
|
||||||
|
qsfp_sync_reset_inst (
|
||||||
|
.clk(qsfp_mgt_refclk_0_bufg),
|
||||||
|
.rst(rst_125mhz),
|
||||||
|
.out(qsfp_rst)
|
||||||
|
);
|
||||||
|
|
||||||
|
taxi_apb_if #(
|
||||||
|
.ADDR_W(18),
|
||||||
|
.DATA_W(16)
|
||||||
|
)
|
||||||
|
gt_apb_ctrl();
|
||||||
|
|
||||||
|
wire ptp_clk = qsfp_mgt_refclk_0_bufg;
|
||||||
|
wire ptp_rst = qsfp_rst;
|
||||||
|
wire ptp_sample_clk = clk_125mhz;
|
||||||
|
wire ptp_td_sd;
|
||||||
|
wire ptp_pps;
|
||||||
|
wire ptp_pps_str;
|
||||||
|
|
||||||
|
assign led[7] = ptp_pps_str;
|
||||||
|
|
||||||
|
taxi_xfcp_mod_apb #(
|
||||||
|
.XFCP_EXT_ID_STR("GTY CTRL")
|
||||||
|
)
|
||||||
|
xfcp_mod_apb_inst (
|
||||||
|
.clk(clk_125mhz),
|
||||||
|
.rst(rst_125mhz),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* XFCP upstream port
|
||||||
|
*/
|
||||||
|
.xfcp_usp_ds(xfcp_sw_ds[1]),
|
||||||
|
.xfcp_usp_us(xfcp_sw_us[1]),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* APB master interface
|
||||||
|
*/
|
||||||
|
.m_apb(gt_apb_ctrl)
|
||||||
|
);
|
||||||
|
|
||||||
|
taxi_eth_mac_25g_us #(
|
||||||
|
.SIM(SIM),
|
||||||
|
.VENDOR(VENDOR),
|
||||||
|
.FAMILY(FAMILY),
|
||||||
|
|
||||||
|
.CNT(4),
|
||||||
|
|
||||||
|
// GT config
|
||||||
|
.CFG_LOW_LATENCY(CFG_LOW_LATENCY),
|
||||||
|
|
||||||
|
// GT type
|
||||||
|
.GT_TYPE("GTY"),
|
||||||
|
|
||||||
|
// MAC/PHY config
|
||||||
|
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
|
||||||
|
.DATA_W(MAC_DATA_W),
|
||||||
|
.PADDING_EN(1'b1),
|
||||||
|
.DIC_EN(1'b1),
|
||||||
|
.MIN_FRAME_LEN(64),
|
||||||
|
.PTP_TS_EN(PTP_TS_EN),
|
||||||
|
.PTP_TD_EN(PTP_TS_EN),
|
||||||
|
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
|
||||||
|
.PTP_TS_W(PTP_TS_W),
|
||||||
|
.PTP_TD_SDI_PIPELINE(2),
|
||||||
|
.PRBS31_EN(1'b0),
|
||||||
|
.TX_SERDES_PIPELINE(1),
|
||||||
|
.RX_SERDES_PIPELINE(1),
|
||||||
|
.COUNT_125US(125000/6.4),
|
||||||
|
.STAT_EN(1),
|
||||||
|
.STAT_TX_LEVEL(1),
|
||||||
|
.STAT_RX_LEVEL(1),
|
||||||
|
.STAT_ID_BASE(16+16),
|
||||||
|
.STAT_UPDATE_PERIOD(1024),
|
||||||
|
.STAT_STR_EN(1),
|
||||||
|
.STAT_PREFIX_STR('{"QSFP.1", "QSFP.2", "QSFP.3", "QSFP.4"})
|
||||||
|
)
|
||||||
|
qsfp_mac_inst (
|
||||||
|
.xcvr_ctrl_clk(clk_125mhz),
|
||||||
|
.xcvr_ctrl_rst(qsfp_rst),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Transceiver control
|
||||||
|
*/
|
||||||
|
.s_apb_ctrl(gt_apb_ctrl),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Common
|
||||||
|
*/
|
||||||
|
.xcvr_gtpowergood_out(qsfp_gtpowergood),
|
||||||
|
.xcvr_gtrefclk00_in(qsfp_mgt_refclk_0),
|
||||||
|
.xcvr_qpll0pd_in(1'b0),
|
||||||
|
.xcvr_qpll0reset_in(1'b0),
|
||||||
|
.xcvr_qpll0pcierate_in(3'd0),
|
||||||
|
.xcvr_qpll0lock_out(),
|
||||||
|
.xcvr_qpll0clk_out(),
|
||||||
|
.xcvr_qpll0refclk_out(),
|
||||||
|
.xcvr_gtrefclk01_in(qsfp_mgt_refclk_0),
|
||||||
|
.xcvr_qpll1pd_in(1'b0),
|
||||||
|
.xcvr_qpll1reset_in(1'b0),
|
||||||
|
.xcvr_qpll1pcierate_in(3'd0),
|
||||||
|
.xcvr_qpll1lock_out(),
|
||||||
|
.xcvr_qpll1clk_out(),
|
||||||
|
.xcvr_qpll1refclk_out(),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Serial data
|
||||||
|
*/
|
||||||
|
.xcvr_txp(qsfp_tx_p),
|
||||||
|
.xcvr_txn(qsfp_tx_n),
|
||||||
|
.xcvr_rxp(qsfp_rx_p),
|
||||||
|
.xcvr_rxn(qsfp_rx_n),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* MAC clocks
|
||||||
|
*/
|
||||||
|
.rx_clk(qsfp_rx_clk),
|
||||||
|
.rx_rst_in('{4{1'b0}}),
|
||||||
|
.rx_rst_out(qsfp_rx_rst),
|
||||||
|
.tx_clk(qsfp_tx_clk),
|
||||||
|
.tx_rst_in('{4{1'b0}}),
|
||||||
|
.tx_rst_out(qsfp_tx_rst),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Transmit interface (AXI stream)
|
||||||
|
*/
|
||||||
|
.s_axis_tx(axis_qsfp_tx),
|
||||||
|
.m_axis_tx_cpl(axis_qsfp_tx_cpl),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Receive interface (AXI stream)
|
||||||
|
*/
|
||||||
|
.m_axis_rx(axis_qsfp_rx),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* PTP clock
|
||||||
|
*/
|
||||||
|
.ptp_clk(ptp_clk),
|
||||||
|
.ptp_rst(ptp_rst),
|
||||||
|
.ptp_sample_clk(ptp_sample_clk),
|
||||||
|
.ptp_td_sdi(ptp_td_sd),
|
||||||
|
.tx_ptp_ts_in('{4{'0}}),
|
||||||
|
.tx_ptp_ts_out(),
|
||||||
|
.tx_ptp_ts_step_out(),
|
||||||
|
.tx_ptp_locked(),
|
||||||
|
.rx_ptp_ts_in('{4{'0}}),
|
||||||
|
.rx_ptp_ts_out(),
|
||||||
|
.rx_ptp_ts_step_out(),
|
||||||
|
.rx_ptp_locked(),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
|
||||||
|
*/
|
||||||
|
.tx_lfc_req('{4{1'b0}}),
|
||||||
|
.tx_lfc_resend('{4{1'b0}}),
|
||||||
|
.rx_lfc_en('{4{1'b0}}),
|
||||||
|
.rx_lfc_req(),
|
||||||
|
.rx_lfc_ack('{4{1'b0}}),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
|
||||||
|
*/
|
||||||
|
.tx_pfc_req('{4{'0}}),
|
||||||
|
.tx_pfc_resend('{4{1'b0}}),
|
||||||
|
.rx_pfc_en('{4{'0}}),
|
||||||
|
.rx_pfc_req(),
|
||||||
|
.rx_pfc_ack('{4{'0}}),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Pause interface
|
||||||
|
*/
|
||||||
|
.tx_lfc_pause_en('{4{1'b0}}),
|
||||||
|
.tx_pause_req('{4{1'b0}}),
|
||||||
|
.tx_pause_ack(),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Statistics
|
||||||
|
*/
|
||||||
|
.stat_clk(clk_125mhz),
|
||||||
|
.stat_rst(rst_125mhz),
|
||||||
|
.m_axis_stat(axis_eth_stat[1]),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Status
|
||||||
|
*/
|
||||||
|
.tx_start_packet(),
|
||||||
|
.stat_tx_byte(),
|
||||||
|
.stat_tx_pkt_len(),
|
||||||
|
.stat_tx_pkt_ucast(),
|
||||||
|
.stat_tx_pkt_mcast(),
|
||||||
|
.stat_tx_pkt_bcast(),
|
||||||
|
.stat_tx_pkt_vlan(),
|
||||||
|
.stat_tx_pkt_good(),
|
||||||
|
.stat_tx_pkt_bad(),
|
||||||
|
.stat_tx_err_oversize(),
|
||||||
|
.stat_tx_err_user(),
|
||||||
|
.stat_tx_err_underflow(),
|
||||||
|
.rx_start_packet(),
|
||||||
|
.rx_error_count(),
|
||||||
|
.rx_block_lock(),
|
||||||
|
.rx_high_ber(),
|
||||||
|
.rx_status(qsfp_rx_status),
|
||||||
|
.stat_rx_byte(),
|
||||||
|
.stat_rx_pkt_len(),
|
||||||
|
.stat_rx_pkt_fragment(),
|
||||||
|
.stat_rx_pkt_jabber(),
|
||||||
|
.stat_rx_pkt_ucast(),
|
||||||
|
.stat_rx_pkt_mcast(),
|
||||||
|
.stat_rx_pkt_bcast(),
|
||||||
|
.stat_rx_pkt_vlan(),
|
||||||
|
.stat_rx_pkt_good(),
|
||||||
|
.stat_rx_pkt_bad(),
|
||||||
|
.stat_rx_err_oversize(),
|
||||||
|
.stat_rx_err_bad_fcs(),
|
||||||
|
.stat_rx_err_bad_block(),
|
||||||
|
.stat_rx_err_framing(),
|
||||||
|
.stat_rx_err_preamble(),
|
||||||
|
.stat_rx_fifo_drop('{4{1'b0}}),
|
||||||
|
.stat_tx_mcf(),
|
||||||
|
.stat_rx_mcf(),
|
||||||
|
.stat_tx_lfc_pkt(),
|
||||||
|
.stat_tx_lfc_xon(),
|
||||||
|
.stat_tx_lfc_xoff(),
|
||||||
|
.stat_tx_lfc_paused(),
|
||||||
|
.stat_tx_pfc_pkt(),
|
||||||
|
.stat_tx_pfc_xon(),
|
||||||
|
.stat_tx_pfc_xoff(),
|
||||||
|
.stat_tx_pfc_paused(),
|
||||||
|
.stat_rx_lfc_pkt(),
|
||||||
|
.stat_rx_lfc_xon(),
|
||||||
|
.stat_rx_lfc_xoff(),
|
||||||
|
.stat_rx_lfc_paused(),
|
||||||
|
.stat_rx_pfc_pkt(),
|
||||||
|
.stat_rx_pfc_xon(),
|
||||||
|
.stat_rx_pfc_xoff(),
|
||||||
|
.stat_rx_pfc_paused(),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Configuration
|
||||||
|
*/
|
||||||
|
.cfg_tx_max_pkt_len('{4{16'd9218}}),
|
||||||
|
.cfg_tx_ifg('{4{8'd12}}),
|
||||||
|
.cfg_tx_enable('{4{1'b1}}),
|
||||||
|
.cfg_rx_max_pkt_len('{4{16'd9218}}),
|
||||||
|
.cfg_rx_enable('{4{1'b1}}),
|
||||||
|
.cfg_tx_prbs31_enable('{4{1'b0}}),
|
||||||
|
.cfg_rx_prbs31_enable('{4{1'b0}}),
|
||||||
|
.cfg_mcf_rx_eth_dst_mcast('{4{48'h01_80_C2_00_00_01}}),
|
||||||
|
.cfg_mcf_rx_check_eth_dst_mcast('{4{1'b1}}),
|
||||||
|
.cfg_mcf_rx_eth_dst_ucast('{4{48'd0}}),
|
||||||
|
.cfg_mcf_rx_check_eth_dst_ucast('{4{1'b0}}),
|
||||||
|
.cfg_mcf_rx_eth_src('{4{48'd0}}),
|
||||||
|
.cfg_mcf_rx_check_eth_src('{4{1'b0}}),
|
||||||
|
.cfg_mcf_rx_eth_type('{4{16'h8808}}),
|
||||||
|
.cfg_mcf_rx_opcode_lfc('{4{16'h0001}}),
|
||||||
|
.cfg_mcf_rx_check_opcode_lfc('{4{1'b1}}),
|
||||||
|
.cfg_mcf_rx_opcode_pfc('{4{16'h0101}}),
|
||||||
|
.cfg_mcf_rx_check_opcode_pfc('{4{1'b1}}),
|
||||||
|
.cfg_mcf_rx_forward('{4{1'b0}}),
|
||||||
|
.cfg_mcf_rx_enable('{4{1'b0}}),
|
||||||
|
.cfg_tx_lfc_eth_dst('{4{48'h01_80_C2_00_00_01}}),
|
||||||
|
.cfg_tx_lfc_eth_src('{4{48'h80_23_31_43_54_4C}}),
|
||||||
|
.cfg_tx_lfc_eth_type('{4{16'h8808}}),
|
||||||
|
.cfg_tx_lfc_opcode('{4{16'h0001}}),
|
||||||
|
.cfg_tx_lfc_en('{4{1'b0}}),
|
||||||
|
.cfg_tx_lfc_quanta('{4{16'hffff}}),
|
||||||
|
.cfg_tx_lfc_refresh('{4{16'h7fff}}),
|
||||||
|
.cfg_tx_pfc_eth_dst('{4{48'h01_80_C2_00_00_01}}),
|
||||||
|
.cfg_tx_pfc_eth_src('{4{48'h80_23_31_43_54_4C}}),
|
||||||
|
.cfg_tx_pfc_eth_type('{4{16'h8808}}),
|
||||||
|
.cfg_tx_pfc_opcode('{4{16'h0101}}),
|
||||||
|
.cfg_tx_pfc_en('{4{1'b0}}),
|
||||||
|
.cfg_tx_pfc_quanta('{4{'{8{16'hffff}}}}),
|
||||||
|
.cfg_tx_pfc_refresh('{4{'{8{16'h7fff}}}}),
|
||||||
|
.cfg_rx_lfc_opcode('{4{16'h0001}}),
|
||||||
|
.cfg_rx_lfc_en('{4{1'b0}}),
|
||||||
|
.cfg_rx_pfc_opcode('{4{16'h0101}}),
|
||||||
|
.cfg_rx_pfc_en('{4{1'b0}})
|
||||||
|
);
|
||||||
|
|
||||||
|
wire [1:0] cfg_interrupt_msi_pending_status_function_num_int;
|
||||||
|
wire [7:0] cfg_interrupt_msi_tph_st_tag_int;
|
||||||
|
wire [7:0] cfg_interrupt_msi_function_number_int;
|
||||||
|
|
||||||
|
assign cfg_interrupt_msi_pending_status_function_num = 4'(cfg_interrupt_msi_pending_status_function_num_int);
|
||||||
|
assign cfg_interrupt_msi_tph_st_tag = 9'(cfg_interrupt_msi_tph_st_tag_int);
|
||||||
|
assign cfg_interrupt_msi_function_number = cfg_interrupt_msi_function_number_int[3:0];
|
||||||
|
|
||||||
|
cndm_micro_pcie_us #(
|
||||||
|
.SIM(SIM),
|
||||||
|
.VENDOR(VENDOR),
|
||||||
|
.FAMILY(FAMILY),
|
||||||
|
|
||||||
|
// FW ID
|
||||||
|
.FPGA_ID(FPGA_ID),
|
||||||
|
.FW_ID(FW_ID),
|
||||||
|
.FW_VER(FW_VER),
|
||||||
|
.BOARD_ID(BOARD_ID),
|
||||||
|
.BOARD_VER(BOARD_VER),
|
||||||
|
.BUILD_DATE(BUILD_DATE),
|
||||||
|
.GIT_HASH(GIT_HASH),
|
||||||
|
.RELEASE_INFO(RELEASE_INFO),
|
||||||
|
|
||||||
|
// Structural configuration
|
||||||
|
.PORTS(4),
|
||||||
|
|
||||||
|
// PTP configuration
|
||||||
|
.PTP_TS_EN(PTP_TS_EN),
|
||||||
|
.PTP_TS_FMT_TOD(1'b0),
|
||||||
|
.PTP_CLK_PER_NS_NUM(32),
|
||||||
|
.PTP_CLK_PER_NS_DENOM(5),
|
||||||
|
|
||||||
|
// PCIe interface configuration
|
||||||
|
.RQ_SEQ_NUM_W(RQ_SEQ_NUM_W),
|
||||||
|
|
||||||
|
// AXI lite interface configuration (control)
|
||||||
|
.AXIL_CTRL_DATA_W(AXIL_CTRL_DATA_W),
|
||||||
|
.AXIL_CTRL_ADDR_W(AXIL_CTRL_ADDR_W)
|
||||||
|
)
|
||||||
|
cndm_inst (
|
||||||
|
/*
|
||||||
|
* PCIe
|
||||||
|
*/
|
||||||
|
.pcie_clk(pcie_clk),
|
||||||
|
.pcie_rst(pcie_rst),
|
||||||
|
.s_axis_pcie_cq(s_axis_pcie_cq),
|
||||||
|
.m_axis_pcie_cc(m_axis_pcie_cc),
|
||||||
|
.m_axis_pcie_rq(m_axis_pcie_rq),
|
||||||
|
.s_axis_pcie_rc(s_axis_pcie_rc),
|
||||||
|
|
||||||
|
.pcie_rq_seq_num0(pcie_rq_seq_num),
|
||||||
|
.pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld),
|
||||||
|
.pcie_rq_seq_num1('0),
|
||||||
|
.pcie_rq_seq_num_vld1('0),
|
||||||
|
|
||||||
|
.cfg_max_payload(cfg_max_payload),
|
||||||
|
.cfg_max_read_req(cfg_max_read_req),
|
||||||
|
.cfg_rcb_status(cfg_rcb_status),
|
||||||
|
|
||||||
|
.cfg_mgmt_addr(cfg_mgmt_addr[9:0]),
|
||||||
|
.cfg_mgmt_function_number(cfg_mgmt_addr[17:10]),
|
||||||
|
.cfg_mgmt_write(cfg_mgmt_write),
|
||||||
|
.cfg_mgmt_write_data(cfg_mgmt_write_data),
|
||||||
|
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
|
||||||
|
.cfg_mgmt_read(cfg_mgmt_read),
|
||||||
|
.cfg_mgmt_read_data(cfg_mgmt_read_data),
|
||||||
|
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
|
||||||
|
|
||||||
|
.cfg_fc_ph(cfg_fc_ph),
|
||||||
|
.cfg_fc_pd(cfg_fc_pd),
|
||||||
|
.cfg_fc_nph(cfg_fc_nph),
|
||||||
|
.cfg_fc_npd(cfg_fc_npd),
|
||||||
|
.cfg_fc_cplh(cfg_fc_cplh),
|
||||||
|
.cfg_fc_cpld(cfg_fc_cpld),
|
||||||
|
.cfg_fc_sel(cfg_fc_sel),
|
||||||
|
|
||||||
|
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||||
|
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||||
|
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||||
|
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||||
|
.cfg_interrupt_msi_select(2'(cfg_interrupt_msi_select)),
|
||||||
|
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||||
|
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||||
|
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||||
|
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num_int),
|
||||||
|
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||||
|
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||||
|
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||||
|
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||||
|
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||||
|
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag_int),
|
||||||
|
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number_int),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* PTP
|
||||||
|
*/
|
||||||
|
.ptp_clk(ptp_clk),
|
||||||
|
.ptp_rst(ptp_rst),
|
||||||
|
.ptp_sample_clk(ptp_sample_clk),
|
||||||
|
.ptp_td_sdo(ptp_td_sd),
|
||||||
|
.ptp_pps(ptp_pps),
|
||||||
|
.ptp_pps_str(ptp_pps_str),
|
||||||
|
.ptp_sync_locked(),
|
||||||
|
.ptp_sync_ts_rel(),
|
||||||
|
.ptp_sync_ts_rel_step(),
|
||||||
|
.ptp_sync_ts_tod(),
|
||||||
|
.ptp_sync_ts_tod_step(),
|
||||||
|
.ptp_sync_pps(),
|
||||||
|
.ptp_sync_pps_str(),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Ethernet
|
||||||
|
*/
|
||||||
|
.mac_tx_clk(qsfp_tx_clk),
|
||||||
|
.mac_tx_rst(qsfp_tx_rst),
|
||||||
|
.mac_axis_tx(axis_qsfp_tx),
|
||||||
|
.mac_axis_tx_cpl(axis_qsfp_tx_cpl),
|
||||||
|
|
||||||
|
.mac_rx_clk(qsfp_rx_clk),
|
||||||
|
.mac_rx_rst(qsfp_rx_rst),
|
||||||
|
.mac_axis_rx(axis_qsfp_rx)
|
||||||
|
);
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
`resetall
|
||||||
75
src/cndm/board/VCU108/fpga/tb/fpga_core/Makefile
Normal file
75
src/cndm/board/VCU108/fpga/tb/fpga_core/Makefile
Normal file
@@ -0,0 +1,75 @@
|
|||||||
|
# SPDX-License-Identifier: MIT
|
||||||
|
#
|
||||||
|
# Copyright (c) 2020-2026 FPGA Ninja, LLC
|
||||||
|
#
|
||||||
|
# Authors:
|
||||||
|
# - Alex Forencich
|
||||||
|
|
||||||
|
TOPLEVEL_LANG = verilog
|
||||||
|
|
||||||
|
SIM ?= verilator
|
||||||
|
WAVES ?= 0
|
||||||
|
|
||||||
|
COCOTB_HDL_TIMEUNIT = 1ns
|
||||||
|
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||||
|
|
||||||
|
RTL_DIR = ../../rtl
|
||||||
|
LIB_DIR = ../../lib
|
||||||
|
TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
|
||||||
|
|
||||||
|
DUT = fpga_core
|
||||||
|
COCOTB_TEST_MODULES = test_$(DUT)
|
||||||
|
COCOTB_TOPLEVEL = test_$(DUT)
|
||||||
|
MODULE = $(COCOTB_TEST_MODULES)
|
||||||
|
TOPLEVEL = $(COCOTB_TOPLEVEL)
|
||||||
|
VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
|
||||||
|
VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
|
||||||
|
VERILOG_SOURCES += $(TAXI_SRC_DIR)/cndm/rtl/cndm_micro_pcie_us.f
|
||||||
|
VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/taxi_eth_mac_1g_fifo.f
|
||||||
|
VERILOG_SOURCES += $(TAXI_SRC_DIR)/eth/rtl/us/taxi_eth_mac_25g_us.f
|
||||||
|
VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_if_uart.f
|
||||||
|
VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_apb.sv
|
||||||
|
VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_switch.sv
|
||||||
|
VERILOG_SOURCES += $(TAXI_SRC_DIR)/xfcp/rtl/taxi_xfcp_mod_stats.f
|
||||||
|
VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_reset.sv
|
||||||
|
VERILOG_SOURCES += $(TAXI_SRC_DIR)/sync/rtl/taxi_sync_signal.sv
|
||||||
|
VERILOG_SOURCES += $(TAXI_SRC_DIR)/io/rtl/taxi_debounce_switch.sv
|
||||||
|
VERILOG_SOURCES += $(TAXI_SRC_DIR)/pyrite/rtl/pyrite_pcie_us_vsec_bpi.f
|
||||||
|
|
||||||
|
# handle file list files
|
||||||
|
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
|
||||||
|
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
|
||||||
|
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
|
||||||
|
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
|
||||||
|
|
||||||
|
# module parameters
|
||||||
|
export PARAM_SIM := "1'b1"
|
||||||
|
export PARAM_VENDOR := "\"XILINX\""
|
||||||
|
export PARAM_FAMILY := "\"virtexu\""
|
||||||
|
|
||||||
|
# PTP configuration
|
||||||
|
export PARAM_PTP_TS_EN := 1
|
||||||
|
|
||||||
|
# AXI lite interface configuration (control)
|
||||||
|
export PARAM_AXIL_CTRL_DATA_W := 32
|
||||||
|
export PARAM_AXIL_CTRL_ADDR_W := 24
|
||||||
|
|
||||||
|
# MAC configuration
|
||||||
|
export PARAM_CFG_LOW_LATENCY := 1
|
||||||
|
export PARAM_COMBINED_MAC_PCS := 1
|
||||||
|
export PARAM_MAC_DATA_W := "64"
|
||||||
|
|
||||||
|
ifeq ($(SIM), icarus)
|
||||||
|
PLUSARGS += -fst
|
||||||
|
|
||||||
|
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
|
||||||
|
else ifeq ($(SIM), verilator)
|
||||||
|
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
|
||||||
|
|
||||||
|
ifeq ($(WAVES), 1)
|
||||||
|
COMPILE_ARGS += --trace-fst
|
||||||
|
VERILATOR_TRACE = 1
|
||||||
|
endif
|
||||||
|
endif
|
||||||
|
|
||||||
|
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||||
1
src/cndm/board/VCU108/fpga/tb/fpga_core/baser.py
Symbolic link
1
src/cndm/board/VCU108/fpga/tb/fpga_core/baser.py
Symbolic link
@@ -0,0 +1 @@
|
|||||||
|
../../lib/taxi/src/eth/tb/baser.py
|
||||||
1
src/cndm/board/VCU108/fpga/tb/fpga_core/cndm.py
Symbolic link
1
src/cndm/board/VCU108/fpga/tb/fpga_core/cndm.py
Symbolic link
@@ -0,0 +1 @@
|
|||||||
|
../../lib/taxi/src/cndm/tb/cndm.py
|
||||||
518
src/cndm/board/VCU108/fpga/tb/fpga_core/test_fpga_core.py
Normal file
518
src/cndm/board/VCU108/fpga/tb/fpga_core/test_fpga_core.py
Normal file
@@ -0,0 +1,518 @@
|
|||||||
|
#!/usr/bin/env python
|
||||||
|
# SPDX-License-Identifier: MIT
|
||||||
|
"""
|
||||||
|
|
||||||
|
Copyright (c) 2020-2026 FPGA Ninja, LLC
|
||||||
|
|
||||||
|
Authors:
|
||||||
|
- Alex Forencich
|
||||||
|
|
||||||
|
"""
|
||||||
|
|
||||||
|
import logging
|
||||||
|
import os
|
||||||
|
import sys
|
||||||
|
|
||||||
|
import pytest
|
||||||
|
import cocotb_test.simulator
|
||||||
|
|
||||||
|
import cocotb
|
||||||
|
from cocotb.clock import Clock
|
||||||
|
from cocotb.triggers import RisingEdge, FallingEdge, Timer
|
||||||
|
|
||||||
|
from cocotbext.axi import AxiStreamBus
|
||||||
|
from cocotbext.eth import GmiiFrame, GmiiSource, GmiiSink
|
||||||
|
from cocotbext.eth import XgmiiFrame
|
||||||
|
from cocotbext.uart import UartSource, UartSink
|
||||||
|
from cocotbext.pcie.core import RootComplex
|
||||||
|
from cocotbext.pcie.xilinx.us import UltraScalePcieDevice
|
||||||
|
|
||||||
|
try:
|
||||||
|
from baser import BaseRSerdesSource, BaseRSerdesSink
|
||||||
|
import cndm
|
||||||
|
except ImportError:
|
||||||
|
# attempt import from current directory
|
||||||
|
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
|
||||||
|
try:
|
||||||
|
from baser import BaseRSerdesSource, BaseRSerdesSink
|
||||||
|
import cndm
|
||||||
|
finally:
|
||||||
|
del sys.path[0]
|
||||||
|
|
||||||
|
|
||||||
|
class TB:
|
||||||
|
def __init__(self, dut, speed=1000e6):
|
||||||
|
self.dut = dut
|
||||||
|
|
||||||
|
self.log = logging.getLogger("cocotb.tb")
|
||||||
|
self.log.setLevel(logging.DEBUG)
|
||||||
|
|
||||||
|
# Clocks
|
||||||
|
cocotb.start_soon(Clock(dut.clk_125mhz, 8, units="ns").start())
|
||||||
|
|
||||||
|
# PCIe
|
||||||
|
self.rc = RootComplex()
|
||||||
|
|
||||||
|
self.rc.max_payload_size = 0x1 # 256 bytes
|
||||||
|
self.rc.max_read_request_size = 0x2 # 512 bytes
|
||||||
|
|
||||||
|
self.dev = UltraScalePcieDevice(
|
||||||
|
# configuration options
|
||||||
|
pcie_generation=3,
|
||||||
|
pcie_link_width=8,
|
||||||
|
user_clk_frequency=250e6,
|
||||||
|
alignment="dword",
|
||||||
|
rc_straddle=False,
|
||||||
|
pf_count=1,
|
||||||
|
max_payload_size=1024,
|
||||||
|
enable_client_tag=True,
|
||||||
|
enable_extended_tag=True,
|
||||||
|
enable_parity=False,
|
||||||
|
enable_rx_msg_interface=False,
|
||||||
|
enable_sriov=False,
|
||||||
|
enable_extended_configuration=False,
|
||||||
|
|
||||||
|
pf0_msi_enable=True,
|
||||||
|
pf0_msi_count=32,
|
||||||
|
pf1_msi_enable=False,
|
||||||
|
pf1_msi_count=1,
|
||||||
|
pf0_msix_enable=False,
|
||||||
|
pf0_msix_table_size=31,
|
||||||
|
pf0_msix_table_bir=4,
|
||||||
|
pf0_msix_table_offset=0x00000000,
|
||||||
|
pf0_msix_pba_bir=4,
|
||||||
|
pf0_msix_pba_offset=0x00008000,
|
||||||
|
pf1_msix_enable=False,
|
||||||
|
pf1_msix_table_size=0,
|
||||||
|
pf1_msix_table_bir=0,
|
||||||
|
pf1_msix_table_offset=0x00000000,
|
||||||
|
pf1_msix_pba_bir=0,
|
||||||
|
pf1_msix_pba_offset=0x00000000,
|
||||||
|
|
||||||
|
# signals
|
||||||
|
# Clock and Reset Interface
|
||||||
|
user_clk=dut.pcie_clk,
|
||||||
|
user_reset=dut.pcie_rst,
|
||||||
|
# user_lnk_up
|
||||||
|
# sys_clk
|
||||||
|
# sys_clk_gt
|
||||||
|
# sys_reset
|
||||||
|
# phy_rdy_out
|
||||||
|
|
||||||
|
# Requester reQuest Interface
|
||||||
|
rq_bus=AxiStreamBus.from_entity(dut.m_axis_pcie_rq),
|
||||||
|
pcie_rq_seq_num=dut.pcie_rq_seq_num,
|
||||||
|
pcie_rq_seq_num_vld=dut.pcie_rq_seq_num_vld,
|
||||||
|
# pcie_rq_tag
|
||||||
|
# pcie_rq_tag_av
|
||||||
|
# pcie_rq_tag_vld
|
||||||
|
|
||||||
|
# Requester Completion Interface
|
||||||
|
rc_bus=AxiStreamBus.from_entity(dut.s_axis_pcie_rc),
|
||||||
|
|
||||||
|
# Completer reQuest Interface
|
||||||
|
cq_bus=AxiStreamBus.from_entity(dut.s_axis_pcie_cq),
|
||||||
|
# pcie_cq_np_req
|
||||||
|
# pcie_cq_np_req_count
|
||||||
|
|
||||||
|
# Completer Completion Interface
|
||||||
|
cc_bus=AxiStreamBus.from_entity(dut.m_axis_pcie_cc),
|
||||||
|
|
||||||
|
# Transmit Flow Control Interface
|
||||||
|
# pcie_tfc_nph_av=dut.pcie_tfc_nph_av,
|
||||||
|
# pcie_tfc_npd_av=dut.pcie_tfc_npd_av,
|
||||||
|
|
||||||
|
# Configuration Management Interface
|
||||||
|
cfg_mgmt_addr=dut.cfg_mgmt_addr,
|
||||||
|
cfg_mgmt_write=dut.cfg_mgmt_write,
|
||||||
|
cfg_mgmt_write_data=dut.cfg_mgmt_write_data,
|
||||||
|
cfg_mgmt_byte_enable=dut.cfg_mgmt_byte_enable,
|
||||||
|
cfg_mgmt_read=dut.cfg_mgmt_read,
|
||||||
|
cfg_mgmt_read_data=dut.cfg_mgmt_read_data,
|
||||||
|
cfg_mgmt_read_write_done=dut.cfg_mgmt_read_write_done,
|
||||||
|
# cfg_mgmt_debug_access
|
||||||
|
|
||||||
|
# Configuration Status Interface
|
||||||
|
# cfg_phy_link_down
|
||||||
|
# cfg_phy_link_status
|
||||||
|
# cfg_negotiated_width
|
||||||
|
# cfg_current_speed
|
||||||
|
cfg_max_payload=dut.cfg_max_payload,
|
||||||
|
cfg_max_read_req=dut.cfg_max_read_req,
|
||||||
|
# cfg_function_status
|
||||||
|
# cfg_vf_status
|
||||||
|
# cfg_function_power_state
|
||||||
|
# cfg_vf_power_state
|
||||||
|
# cfg_link_power_state
|
||||||
|
# cfg_err_cor_out
|
||||||
|
# cfg_err_nonfatal_out
|
||||||
|
# cfg_err_fatal_out
|
||||||
|
# cfg_local_error_out
|
||||||
|
# cfg_local_error_valid
|
||||||
|
# cfg_rx_pm_state
|
||||||
|
# cfg_tx_pm_state
|
||||||
|
# cfg_ltssm_state
|
||||||
|
cfg_rcb_status=dut.cfg_rcb_status,
|
||||||
|
# cfg_obff_enable
|
||||||
|
# cfg_pl_status_change
|
||||||
|
# cfg_tph_requester_enable
|
||||||
|
# cfg_tph_st_mode
|
||||||
|
# cfg_vf_tph_requester_enable
|
||||||
|
# cfg_vf_tph_st_mode
|
||||||
|
|
||||||
|
# Configuration Received Message Interface
|
||||||
|
# cfg_msg_received
|
||||||
|
# cfg_msg_received_data
|
||||||
|
# cfg_msg_received_type
|
||||||
|
|
||||||
|
# Configuration Transmit Message Interface
|
||||||
|
# cfg_msg_transmit
|
||||||
|
# cfg_msg_transmit_type
|
||||||
|
# cfg_msg_transmit_data
|
||||||
|
# cfg_msg_transmit_done
|
||||||
|
|
||||||
|
# Configuration Flow Control Interface
|
||||||
|
cfg_fc_ph=dut.cfg_fc_ph,
|
||||||
|
cfg_fc_pd=dut.cfg_fc_pd,
|
||||||
|
cfg_fc_nph=dut.cfg_fc_nph,
|
||||||
|
cfg_fc_npd=dut.cfg_fc_npd,
|
||||||
|
cfg_fc_cplh=dut.cfg_fc_cplh,
|
||||||
|
cfg_fc_cpld=dut.cfg_fc_cpld,
|
||||||
|
cfg_fc_sel=dut.cfg_fc_sel,
|
||||||
|
|
||||||
|
# Configuration Control Interface
|
||||||
|
# cfg_hot_reset_in
|
||||||
|
# cfg_hot_reset_out
|
||||||
|
# cfg_config_space_enable
|
||||||
|
# cfg_dsn
|
||||||
|
# cfg_bus_number
|
||||||
|
# cfg_ds_port_number
|
||||||
|
# cfg_ds_bus_number
|
||||||
|
# cfg_ds_device_number
|
||||||
|
# cfg_ds_function_number
|
||||||
|
# cfg_power_state_change_ack
|
||||||
|
# cfg_power_state_change_interrupt
|
||||||
|
# cfg_err_cor_in=dut.status_error_cor,
|
||||||
|
# cfg_err_uncor_in=dut.status_error_uncor,
|
||||||
|
# cfg_flr_in_process
|
||||||
|
# cfg_flr_done
|
||||||
|
# cfg_vf_flr_in_process
|
||||||
|
# cfg_vf_flr_func_num
|
||||||
|
# cfg_vf_flr_done
|
||||||
|
# cfg_pm_aspm_l1_entry_reject
|
||||||
|
# cfg_pm_aspm_tx_l0s_entry_disable
|
||||||
|
# cfg_req_pm_transition_l23_ready
|
||||||
|
# cfg_link_training_enable
|
||||||
|
|
||||||
|
# Configuration Interrupt Controller Interface
|
||||||
|
# cfg_interrupt_int
|
||||||
|
# cfg_interrupt_sent
|
||||||
|
# cfg_interrupt_pending
|
||||||
|
cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable,
|
||||||
|
# cfg_interrupt_msi_vf_enable=dut.cfg_interrupt_msi_vf_enable,
|
||||||
|
cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable,
|
||||||
|
cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update,
|
||||||
|
cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data,
|
||||||
|
cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select,
|
||||||
|
cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int,
|
||||||
|
cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status,
|
||||||
|
cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable,
|
||||||
|
cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num,
|
||||||
|
cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent,
|
||||||
|
cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail,
|
||||||
|
# cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable,
|
||||||
|
# cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask,
|
||||||
|
# cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable,
|
||||||
|
# cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask,
|
||||||
|
# cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address,
|
||||||
|
# cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data,
|
||||||
|
# cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int,
|
||||||
|
# cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent,
|
||||||
|
# cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail,
|
||||||
|
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||||
|
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||||
|
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||||
|
cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag,
|
||||||
|
cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
|
||||||
|
|
||||||
|
# Configuration Extend Interface
|
||||||
|
# cfg_ext_read_received
|
||||||
|
# cfg_ext_write_received
|
||||||
|
# cfg_ext_register_number
|
||||||
|
# cfg_ext_function_number
|
||||||
|
# cfg_ext_write_data
|
||||||
|
# cfg_ext_write_byte_enable
|
||||||
|
# cfg_ext_read_data
|
||||||
|
# cfg_ext_read_data_valid
|
||||||
|
)
|
||||||
|
|
||||||
|
# self.dev.log.setLevel(logging.DEBUG)
|
||||||
|
|
||||||
|
self.rc.make_port().connect(self.dev)
|
||||||
|
|
||||||
|
self.dev.functions[0].configure_bar(0, 2**int(dut.uut.cndm_inst.axil_ctrl_bar.ADDR_W))
|
||||||
|
|
||||||
|
# Ethernet
|
||||||
|
cocotb.start_soon(Clock(dut.phy_gmii_clk, 8, units="ns").start())
|
||||||
|
cocotb.start_soon(Clock(dut.qsfp_mgt_refclk_0_p, 6.4, units="ns").start())
|
||||||
|
|
||||||
|
self.gmii_source = GmiiSource(dut.phy_gmii_rxd, dut.phy_gmii_rx_er, dut.phy_gmii_rx_dv,
|
||||||
|
dut.phy_gmii_clk, dut.phy_gmii_rst, dut.phy_gmii_clk_en)
|
||||||
|
self.gmii_sink = GmiiSink(dut.phy_gmii_txd, dut.phy_gmii_tx_er, dut.phy_gmii_tx_en,
|
||||||
|
dut.phy_gmii_clk, dut.phy_gmii_rst, dut.phy_gmii_clk_en)
|
||||||
|
|
||||||
|
self.uart_source = UartSource(dut.uart_rxd, baud=921600, bits=8, stop_bits=1)
|
||||||
|
self.uart_sink = UartSink(dut.uart_txd, baud=921600, bits=8, stop_bits=1)
|
||||||
|
|
||||||
|
self.qsfp_sources = []
|
||||||
|
self.qsfp_sinks = []
|
||||||
|
|
||||||
|
for ch in dut.uut.qsfp_mac_inst.ch:
|
||||||
|
gt_inst = ch.ch_inst.gt.gt_inst
|
||||||
|
|
||||||
|
if ch.ch_inst.DATA_W.value == 64:
|
||||||
|
if ch.ch_inst.CFG_LOW_LATENCY.value:
|
||||||
|
clk = 2.482
|
||||||
|
gbx_cfg = (66, [64, 65])
|
||||||
|
else:
|
||||||
|
clk = 2.56
|
||||||
|
gbx_cfg = None
|
||||||
|
else:
|
||||||
|
if ch.ch_inst.CFG_LOW_LATENCY.value:
|
||||||
|
clk = 3.102
|
||||||
|
gbx_cfg = (66, [64, 65])
|
||||||
|
else:
|
||||||
|
clk = 3.2
|
||||||
|
gbx_cfg = None
|
||||||
|
|
||||||
|
cocotb.start_soon(Clock(gt_inst.tx_clk, clk, units="ns").start())
|
||||||
|
cocotb.start_soon(Clock(gt_inst.rx_clk, clk, units="ns").start())
|
||||||
|
|
||||||
|
self.qsfp_sources.append(BaseRSerdesSource(
|
||||||
|
data=gt_inst.serdes_rx_data,
|
||||||
|
data_valid=gt_inst.serdes_rx_data_valid,
|
||||||
|
hdr=gt_inst.serdes_rx_hdr,
|
||||||
|
hdr_valid=gt_inst.serdes_rx_hdr_valid,
|
||||||
|
clock=gt_inst.rx_clk,
|
||||||
|
slip=gt_inst.serdes_rx_bitslip,
|
||||||
|
reverse=True,
|
||||||
|
gbx_cfg=gbx_cfg
|
||||||
|
))
|
||||||
|
self.qsfp_sinks.append(BaseRSerdesSink(
|
||||||
|
data=gt_inst.serdes_tx_data,
|
||||||
|
data_valid=gt_inst.serdes_tx_data_valid,
|
||||||
|
hdr=gt_inst.serdes_tx_hdr,
|
||||||
|
hdr_valid=gt_inst.serdes_tx_hdr_valid,
|
||||||
|
gbx_sync=gt_inst.serdes_tx_gbx_sync,
|
||||||
|
clock=gt_inst.tx_clk,
|
||||||
|
reverse=True,
|
||||||
|
gbx_cfg=gbx_cfg
|
||||||
|
))
|
||||||
|
|
||||||
|
dut.phy_gmii_clk_en.setimmediatevalue(1)
|
||||||
|
|
||||||
|
dut.btnu.setimmediatevalue(0)
|
||||||
|
dut.btnl.setimmediatevalue(0)
|
||||||
|
dut.btnd.setimmediatevalue(0)
|
||||||
|
dut.btnr.setimmediatevalue(0)
|
||||||
|
dut.btnc.setimmediatevalue(0)
|
||||||
|
dut.sw.setimmediatevalue(0)
|
||||||
|
dut.uart_rts.setimmediatevalue(0)
|
||||||
|
|
||||||
|
self.loopback_enable = False
|
||||||
|
cocotb.start_soon(self._run_loopback())
|
||||||
|
|
||||||
|
async def init(self):
|
||||||
|
|
||||||
|
self.dut.rst_125mhz.setimmediatevalue(0)
|
||||||
|
self.dut.phy_gmii_rst.setimmediatevalue(0)
|
||||||
|
|
||||||
|
await FallingEdge(self.dut.pcie_rst)
|
||||||
|
await Timer(100, 'ns')
|
||||||
|
|
||||||
|
for k in range(10):
|
||||||
|
await RisingEdge(self.dut.clk_125mhz)
|
||||||
|
|
||||||
|
self.dut.rst_125mhz.value = 1
|
||||||
|
self.dut.phy_gmii_rst.value = 1
|
||||||
|
|
||||||
|
for k in range(10):
|
||||||
|
await RisingEdge(self.dut.clk_125mhz)
|
||||||
|
|
||||||
|
self.dut.rst_125mhz.value = 0
|
||||||
|
self.dut.phy_gmii_rst.value = 0
|
||||||
|
|
||||||
|
for k in range(10):
|
||||||
|
await RisingEdge(self.dut.clk_125mhz)
|
||||||
|
|
||||||
|
await self.rc.enumerate()
|
||||||
|
|
||||||
|
async def _run_loopback(self):
|
||||||
|
while True:
|
||||||
|
await RisingEdge(self.dut.pcie_clk)
|
||||||
|
|
||||||
|
if self.loopback_enable:
|
||||||
|
for src, snk in zip(self.qsfp_sources, self.qsfp_sinks):
|
||||||
|
while not snk.empty():
|
||||||
|
await src.send(await snk.recv())
|
||||||
|
|
||||||
|
@cocotb.test()
|
||||||
|
async def run_test(dut):
|
||||||
|
|
||||||
|
tb = TB(dut)
|
||||||
|
|
||||||
|
await tb.init()
|
||||||
|
|
||||||
|
tb.log.info("Init driver model")
|
||||||
|
driver = cndm.Driver()
|
||||||
|
await driver.init_pcie_dev(tb.rc.find_device(tb.dev.functions[0].pcie_id))
|
||||||
|
|
||||||
|
tb.log.info("Init complete")
|
||||||
|
|
||||||
|
tb.log.info("Wait for block lock")
|
||||||
|
for k in range(1200):
|
||||||
|
await RisingEdge(tb.dut.clk_125mhz)
|
||||||
|
|
||||||
|
for snk in tb.qsfp_sinks:
|
||||||
|
snk.clear()
|
||||||
|
|
||||||
|
tb.log.info("Send and receive single packet on each port")
|
||||||
|
|
||||||
|
for k in range(len(driver.ports)):
|
||||||
|
data = f"Corundum rocks on port {k}!".encode('ascii')
|
||||||
|
|
||||||
|
await driver.ports[k].start_xmit(data)
|
||||||
|
|
||||||
|
pkt = await tb.qsfp_sinks[k].recv()
|
||||||
|
tb.log.info("Got TX packet: %s", pkt)
|
||||||
|
|
||||||
|
assert pkt.get_payload() == data.ljust(60, b'\x00')
|
||||||
|
assert pkt.check_fcs()
|
||||||
|
|
||||||
|
await tb.qsfp_sources[k].send(pkt)
|
||||||
|
|
||||||
|
pkt = await driver.ports[k].recv()
|
||||||
|
tb.log.info("Got RX packet: %s", pkt)
|
||||||
|
|
||||||
|
assert bytes(pkt) == data.ljust(60, b'\x00')
|
||||||
|
|
||||||
|
tb.log.info("Multiple small packets")
|
||||||
|
|
||||||
|
count = 64
|
||||||
|
pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
|
||||||
|
|
||||||
|
tb.loopback_enable = True
|
||||||
|
|
||||||
|
for p in pkts:
|
||||||
|
await driver.ports[0].start_xmit(p)
|
||||||
|
|
||||||
|
for k in range(count):
|
||||||
|
pkt = await driver.ports[0].recv()
|
||||||
|
|
||||||
|
tb.log.info("Got RX packet: %s", pkt)
|
||||||
|
|
||||||
|
assert bytes(pkt) == pkts[k].ljust(60, b'\x00')
|
||||||
|
|
||||||
|
tb.loopback_enable = False
|
||||||
|
|
||||||
|
tb.log.info("Multiple large packets")
|
||||||
|
|
||||||
|
count = 64
|
||||||
|
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
|
||||||
|
|
||||||
|
tb.loopback_enable = True
|
||||||
|
|
||||||
|
for p in pkts:
|
||||||
|
await driver.ports[0].start_xmit(p)
|
||||||
|
|
||||||
|
for k in range(count):
|
||||||
|
pkt = await driver.ports[0].recv()
|
||||||
|
|
||||||
|
tb.log.info("Got RX packet: %s", pkt)
|
||||||
|
|
||||||
|
assert bytes(pkt) == pkts[k].ljust(60, b'\x00')
|
||||||
|
|
||||||
|
tb.loopback_enable = False
|
||||||
|
|
||||||
|
await RisingEdge(dut.clk_125mhz)
|
||||||
|
await RisingEdge(dut.clk_125mhz)
|
||||||
|
|
||||||
|
|
||||||
|
# cocotb-test
|
||||||
|
|
||||||
|
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||||
|
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||||
|
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||||
|
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||||
|
|
||||||
|
|
||||||
|
def process_f_files(files):
|
||||||
|
lst = {}
|
||||||
|
for f in files:
|
||||||
|
if f[-2:].lower() == '.f':
|
||||||
|
with open(f, 'r') as fp:
|
||||||
|
l = fp.read().split()
|
||||||
|
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||||
|
lst[os.path.basename(f)] = f
|
||||||
|
else:
|
||||||
|
lst[os.path.basename(f)] = f
|
||||||
|
return list(lst.values())
|
||||||
|
|
||||||
|
|
||||||
|
@pytest.mark.parametrize("mac_data_w", [32, 64])
|
||||||
|
def test_fpga_core(request, mac_data_w):
|
||||||
|
dut = "fpga_core"
|
||||||
|
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||||
|
toplevel = module
|
||||||
|
|
||||||
|
verilog_sources = [
|
||||||
|
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||||
|
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||||
|
os.path.join(taxi_src_dir, "cndm", "rtl", "cndm_micro_pcie_us.f"),
|
||||||
|
os.path.join(taxi_src_dir, "eth", "rtl", "taxi_eth_mac_1g_fifo.f"),
|
||||||
|
os.path.join(taxi_src_dir, "eth", "rtl", "us", "taxi_eth_mac_25g_us.f"),
|
||||||
|
os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_if_uart.f"),
|
||||||
|
os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_switch.sv"),
|
||||||
|
os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_apb.f"),
|
||||||
|
os.path.join(taxi_src_dir, "xfcp", "rtl", "taxi_xfcp_mod_stats.f"),
|
||||||
|
os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_reset.sv"),
|
||||||
|
os.path.join(taxi_src_dir, "sync", "rtl", "taxi_sync_signal.sv"),
|
||||||
|
os.path.join(taxi_src_dir, "io", "rtl", "taxi_debounce_switch.sv"),
|
||||||
|
os.path.join(taxi_src_dir, "pyrite", "rtl", "pyrite_pcie_us_vsec_bpi.f"),
|
||||||
|
]
|
||||||
|
|
||||||
|
verilog_sources = process_f_files(verilog_sources)
|
||||||
|
|
||||||
|
parameters = {}
|
||||||
|
|
||||||
|
parameters['SIM'] = "1'b1"
|
||||||
|
parameters['VENDOR'] = "\"XILINX\""
|
||||||
|
parameters['FAMILY'] = "\"virtexu\""
|
||||||
|
|
||||||
|
# PTP configuration
|
||||||
|
parameters['PTP_TS_EN'] = 1
|
||||||
|
|
||||||
|
# AXI lite interface configuration (control)
|
||||||
|
parameters['AXIL_CTRL_DATA_W'] = 32
|
||||||
|
parameters['AXIL_CTRL_ADDR_W'] = 24
|
||||||
|
|
||||||
|
# MAC configuration
|
||||||
|
parameters['CFG_LOW_LATENCY'] = 1
|
||||||
|
parameters['COMBINED_MAC_PCS'] = 1
|
||||||
|
parameters['MAC_DATA_W'] = mac_data_w
|
||||||
|
|
||||||
|
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||||
|
|
||||||
|
sim_build = os.path.join(tests_dir, "sim_build",
|
||||||
|
request.node.name.replace('[', '-').replace(']', ''))
|
||||||
|
|
||||||
|
cocotb_test.simulator.run(
|
||||||
|
simulator="verilator",
|
||||||
|
python_search=[tests_dir],
|
||||||
|
verilog_sources=verilog_sources,
|
||||||
|
toplevel=toplevel,
|
||||||
|
module=module,
|
||||||
|
parameters=parameters,
|
||||||
|
sim_build=sim_build,
|
||||||
|
extra_env=extra_env,
|
||||||
|
)
|
||||||
356
src/cndm/board/VCU108/fpga/tb/fpga_core/test_fpga_core.sv
Normal file
356
src/cndm/board/VCU108/fpga/tb/fpga_core/test_fpga_core.sv
Normal file
@@ -0,0 +1,356 @@
|
|||||||
|
// SPDX-License-Identifier: MIT
|
||||||
|
/*
|
||||||
|
|
||||||
|
Copyright (c) 2026 FPGA Ninja, LLC
|
||||||
|
|
||||||
|
Authors:
|
||||||
|
- Alex Forencich
|
||||||
|
|
||||||
|
*/
|
||||||
|
|
||||||
|
`resetall
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
`default_nettype none
|
||||||
|
|
||||||
|
/*
|
||||||
|
* FPGA core logic testbench
|
||||||
|
*/
|
||||||
|
module test_fpga_core #
|
||||||
|
(
|
||||||
|
/* verilator lint_off WIDTHTRUNC */
|
||||||
|
parameter logic SIM = 1'b0,
|
||||||
|
parameter string VENDOR = "XILINX",
|
||||||
|
parameter string FAMILY = "virtexu",
|
||||||
|
|
||||||
|
// FW ID
|
||||||
|
parameter FPGA_ID = 32'h3842093,
|
||||||
|
parameter FW_ID = 32'h0000C001,
|
||||||
|
parameter FW_VER = 32'h000_01_000,
|
||||||
|
parameter BOARD_ID = 32'h10ee_806c,
|
||||||
|
parameter BOARD_VER = 32'h001_00_000,
|
||||||
|
parameter BUILD_DATE = 32'd602976000,
|
||||||
|
parameter GIT_HASH = 32'h5f87c2e8,
|
||||||
|
parameter RELEASE_INFO = 32'h00000000,
|
||||||
|
|
||||||
|
// PTP configuration
|
||||||
|
parameter logic PTP_TS_EN = 1'b1,
|
||||||
|
|
||||||
|
// PCIe interface configuration
|
||||||
|
parameter AXIS_PCIE_DATA_W = 256,
|
||||||
|
parameter AXIS_PCIE_RC_USER_W = 75,
|
||||||
|
parameter AXIS_PCIE_RQ_USER_W = 60,
|
||||||
|
parameter AXIS_PCIE_CQ_USER_W = 85,
|
||||||
|
parameter AXIS_PCIE_CC_USER_W = 33,
|
||||||
|
|
||||||
|
// AXI lite interface configuration (control)
|
||||||
|
parameter AXIL_CTRL_DATA_W = 32,
|
||||||
|
parameter AXIL_CTRL_ADDR_W = 24,
|
||||||
|
|
||||||
|
// MAC configuration
|
||||||
|
parameter logic CFG_LOW_LATENCY = 1'b1,
|
||||||
|
parameter logic COMBINED_MAC_PCS = 1'b1,
|
||||||
|
parameter MAC_DATA_W = 64
|
||||||
|
/* verilator lint_on WIDTHTRUNC */
|
||||||
|
)
|
||||||
|
();
|
||||||
|
|
||||||
|
localparam AXIS_PCIE_KEEP_W = (AXIS_PCIE_DATA_W/32);
|
||||||
|
localparam RQ_SEQ_NUM_W = AXIS_PCIE_RQ_USER_W == 60 ? 4 : 6;
|
||||||
|
|
||||||
|
logic clk_125mhz;
|
||||||
|
logic rst_125mhz;
|
||||||
|
|
||||||
|
logic btnu;
|
||||||
|
logic btnl;
|
||||||
|
logic btnd;
|
||||||
|
logic btnr;
|
||||||
|
logic btnc;
|
||||||
|
logic [3:0] sw;
|
||||||
|
logic [7:0] led;
|
||||||
|
|
||||||
|
logic uart_rxd;
|
||||||
|
logic uart_txd;
|
||||||
|
logic uart_rts;
|
||||||
|
logic uart_cts;
|
||||||
|
|
||||||
|
logic phy_gmii_clk;
|
||||||
|
logic phy_gmii_rst;
|
||||||
|
logic phy_gmii_clk_en;
|
||||||
|
logic [7:0] phy_gmii_rxd;
|
||||||
|
logic phy_gmii_rx_dv;
|
||||||
|
logic phy_gmii_rx_er;
|
||||||
|
logic [7:0] phy_gmii_txd;
|
||||||
|
logic phy_gmii_tx_en;
|
||||||
|
logic phy_gmii_tx_er;
|
||||||
|
logic phy_reset_n;
|
||||||
|
logic phy_int_n;
|
||||||
|
|
||||||
|
logic qsfp_mgt_refclk_0_p;
|
||||||
|
logic qsfp_mgt_refclk_0_n;
|
||||||
|
logic qsfp_modsell;
|
||||||
|
logic qsfp_resetl;
|
||||||
|
logic qsfp_modprsl;
|
||||||
|
logic qsfp_intl;
|
||||||
|
logic qsfp_lpmode;
|
||||||
|
|
||||||
|
logic pcie_clk;
|
||||||
|
logic pcie_rst;
|
||||||
|
|
||||||
|
taxi_axis_if #(
|
||||||
|
.DATA_W(AXIS_PCIE_DATA_W),
|
||||||
|
.KEEP_EN(1),
|
||||||
|
.KEEP_W(AXIS_PCIE_KEEP_W),
|
||||||
|
.USER_EN(1),
|
||||||
|
.USER_W(AXIS_PCIE_CQ_USER_W)
|
||||||
|
) s_axis_pcie_cq();
|
||||||
|
|
||||||
|
taxi_axis_if #(
|
||||||
|
.DATA_W(AXIS_PCIE_DATA_W),
|
||||||
|
.KEEP_EN(1),
|
||||||
|
.KEEP_W(AXIS_PCIE_KEEP_W),
|
||||||
|
.USER_EN(1),
|
||||||
|
.USER_W(AXIS_PCIE_CC_USER_W)
|
||||||
|
) m_axis_pcie_cc();
|
||||||
|
|
||||||
|
taxi_axis_if #(
|
||||||
|
.DATA_W(AXIS_PCIE_DATA_W),
|
||||||
|
.KEEP_EN(1),
|
||||||
|
.KEEP_W(AXIS_PCIE_KEEP_W),
|
||||||
|
.USER_EN(1),
|
||||||
|
.USER_W(AXIS_PCIE_RQ_USER_W)
|
||||||
|
) m_axis_pcie_rq();
|
||||||
|
|
||||||
|
taxi_axis_if #(
|
||||||
|
.DATA_W(AXIS_PCIE_DATA_W),
|
||||||
|
.KEEP_EN(1),
|
||||||
|
.KEEP_W(AXIS_PCIE_KEEP_W),
|
||||||
|
.USER_EN(1),
|
||||||
|
.USER_W(AXIS_PCIE_RC_USER_W)
|
||||||
|
) s_axis_pcie_rc();
|
||||||
|
|
||||||
|
logic [RQ_SEQ_NUM_W-1:0] pcie_rq_seq_num;
|
||||||
|
logic pcie_rq_seq_num_vld;
|
||||||
|
|
||||||
|
logic [2:0] cfg_max_payload;
|
||||||
|
logic [2:0] cfg_max_read_req;
|
||||||
|
logic [3:0] cfg_rcb_status;
|
||||||
|
|
||||||
|
logic [18:0] cfg_mgmt_addr;
|
||||||
|
logic cfg_mgmt_write;
|
||||||
|
logic [31:0] cfg_mgmt_write_data;
|
||||||
|
logic [3:0] cfg_mgmt_byte_enable;
|
||||||
|
logic cfg_mgmt_read;
|
||||||
|
logic [31:0] cfg_mgmt_read_data;
|
||||||
|
logic cfg_mgmt_read_write_done;
|
||||||
|
|
||||||
|
logic [7:0] cfg_fc_ph;
|
||||||
|
logic [11:0] cfg_fc_pd;
|
||||||
|
logic [7:0] cfg_fc_nph;
|
||||||
|
logic [11:0] cfg_fc_npd;
|
||||||
|
logic [7:0] cfg_fc_cplh;
|
||||||
|
logic [11:0] cfg_fc_cpld;
|
||||||
|
logic [2:0] cfg_fc_sel;
|
||||||
|
|
||||||
|
logic cfg_ext_read_received;
|
||||||
|
logic cfg_ext_write_received;
|
||||||
|
logic [9:0] cfg_ext_register_number;
|
||||||
|
logic [7:0] cfg_ext_function_number;
|
||||||
|
logic [31:0] cfg_ext_write_data;
|
||||||
|
logic [3:0] cfg_ext_write_byte_enable;
|
||||||
|
logic [31:0] cfg_ext_read_data;
|
||||||
|
logic cfg_ext_read_data_valid;
|
||||||
|
|
||||||
|
logic [3:0] cfg_interrupt_msi_enable;
|
||||||
|
logic [11:0] cfg_interrupt_msi_mmenable;
|
||||||
|
logic cfg_interrupt_msi_mask_update;
|
||||||
|
logic [31:0] cfg_interrupt_msi_data;
|
||||||
|
logic [3:0] cfg_interrupt_msi_select;
|
||||||
|
logic [31:0] cfg_interrupt_msi_int;
|
||||||
|
logic [31:0] cfg_interrupt_msi_pending_status;
|
||||||
|
logic cfg_interrupt_msi_pending_status_data_enable;
|
||||||
|
logic [3:0] cfg_interrupt_msi_pending_status_function_num;
|
||||||
|
logic cfg_interrupt_msi_sent;
|
||||||
|
logic cfg_interrupt_msi_fail;
|
||||||
|
logic [2:0] cfg_interrupt_msi_attr;
|
||||||
|
logic cfg_interrupt_msi_tph_present;
|
||||||
|
logic [1:0] cfg_interrupt_msi_tph_type;
|
||||||
|
logic [8:0] cfg_interrupt_msi_tph_st_tag;
|
||||||
|
logic [3:0] cfg_interrupt_msi_function_number;
|
||||||
|
|
||||||
|
logic fpga_boot;
|
||||||
|
logic [15:0] flash_dq_i;
|
||||||
|
logic [15:0] flash_dq_o;
|
||||||
|
logic flash_dq_oe;
|
||||||
|
logic [23:0] flash_addr;
|
||||||
|
logic [1:0] flash_region;
|
||||||
|
logic flash_region_oe;
|
||||||
|
logic flash_ce_n;
|
||||||
|
logic flash_oe_n;
|
||||||
|
logic flash_we_n;
|
||||||
|
logic flash_adv_n;
|
||||||
|
|
||||||
|
fpga_core #(
|
||||||
|
.SIM(SIM),
|
||||||
|
.VENDOR(VENDOR),
|
||||||
|
.FAMILY(FAMILY),
|
||||||
|
|
||||||
|
// FW ID
|
||||||
|
.FPGA_ID(FPGA_ID),
|
||||||
|
.FW_ID(FW_ID),
|
||||||
|
.FW_VER(FW_VER),
|
||||||
|
.BOARD_ID(BOARD_ID),
|
||||||
|
.BOARD_VER(BOARD_VER),
|
||||||
|
.BUILD_DATE(BUILD_DATE),
|
||||||
|
.GIT_HASH(GIT_HASH),
|
||||||
|
.RELEASE_INFO(RELEASE_INFO),
|
||||||
|
|
||||||
|
// PTP configuration
|
||||||
|
.PTP_TS_EN(PTP_TS_EN),
|
||||||
|
|
||||||
|
// PCIe interface configuration
|
||||||
|
.RQ_SEQ_NUM_W(RQ_SEQ_NUM_W),
|
||||||
|
|
||||||
|
// AXI lite interface configuration (control)
|
||||||
|
.AXIL_CTRL_DATA_W(AXIL_CTRL_DATA_W),
|
||||||
|
.AXIL_CTRL_ADDR_W(AXIL_CTRL_ADDR_W),
|
||||||
|
|
||||||
|
// MAC configuration
|
||||||
|
.CFG_LOW_LATENCY(CFG_LOW_LATENCY),
|
||||||
|
.COMBINED_MAC_PCS(COMBINED_MAC_PCS),
|
||||||
|
.MAC_DATA_W(MAC_DATA_W)
|
||||||
|
)
|
||||||
|
uut (
|
||||||
|
/*
|
||||||
|
* Clock: 125MHz
|
||||||
|
* Synchronous reset
|
||||||
|
*/
|
||||||
|
.clk_125mhz(clk_125mhz),
|
||||||
|
.rst_125mhz(rst_125mhz),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* GPIO
|
||||||
|
*/
|
||||||
|
.btnu(btnu),
|
||||||
|
.btnl(btnl),
|
||||||
|
.btnd(btnd),
|
||||||
|
.btnr(btnr),
|
||||||
|
.btnc(btnc),
|
||||||
|
.sw(sw),
|
||||||
|
.led(led),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* UART: 115200 bps, 8N1
|
||||||
|
*/
|
||||||
|
.uart_rxd(uart_rxd),
|
||||||
|
.uart_txd(uart_txd),
|
||||||
|
.uart_rts(uart_rts),
|
||||||
|
.uart_cts(uart_cts),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Ethernet: 1000BASE-T SGMII
|
||||||
|
*/
|
||||||
|
.phy_gmii_clk(phy_gmii_clk),
|
||||||
|
.phy_gmii_rst(phy_gmii_rst),
|
||||||
|
.phy_gmii_clk_en(phy_gmii_clk_en),
|
||||||
|
.phy_gmii_rxd(phy_gmii_rxd),
|
||||||
|
.phy_gmii_rx_dv(phy_gmii_rx_dv),
|
||||||
|
.phy_gmii_rx_er(phy_gmii_rx_er),
|
||||||
|
.phy_gmii_txd(phy_gmii_txd),
|
||||||
|
.phy_gmii_tx_en(phy_gmii_tx_en),
|
||||||
|
.phy_gmii_tx_er(phy_gmii_tx_er),
|
||||||
|
.phy_reset_n(phy_reset_n),
|
||||||
|
.phy_int_n(phy_int_n),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Ethernet: QSFP28
|
||||||
|
*/
|
||||||
|
.qsfp_rx_p('{4{1'b0}}),
|
||||||
|
.qsfp_rx_n('{4{1'b0}}),
|
||||||
|
.qsfp_tx_p(),
|
||||||
|
.qsfp_tx_n(),
|
||||||
|
.qsfp_mgt_refclk_0_p(qsfp_mgt_refclk_0_p),
|
||||||
|
.qsfp_mgt_refclk_0_n(qsfp_mgt_refclk_0_n),
|
||||||
|
.qsfp_modsell(qsfp_modsell),
|
||||||
|
.qsfp_resetl(qsfp_resetl),
|
||||||
|
.qsfp_modprsl(qsfp_modprsl),
|
||||||
|
.qsfp_intl(qsfp_intl),
|
||||||
|
.qsfp_lpmode(qsfp_lpmode),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* PCIe
|
||||||
|
*/
|
||||||
|
.pcie_clk(pcie_clk),
|
||||||
|
.pcie_rst(pcie_rst),
|
||||||
|
.s_axis_pcie_cq(s_axis_pcie_cq),
|
||||||
|
.m_axis_pcie_cc(m_axis_pcie_cc),
|
||||||
|
.m_axis_pcie_rq(m_axis_pcie_rq),
|
||||||
|
.s_axis_pcie_rc(s_axis_pcie_rc),
|
||||||
|
|
||||||
|
.pcie_rq_seq_num(pcie_rq_seq_num),
|
||||||
|
.pcie_rq_seq_num_vld(pcie_rq_seq_num_vld),
|
||||||
|
|
||||||
|
.cfg_max_payload(cfg_max_payload),
|
||||||
|
.cfg_max_read_req(cfg_max_read_req),
|
||||||
|
.cfg_rcb_status(cfg_rcb_status),
|
||||||
|
|
||||||
|
.cfg_mgmt_addr(cfg_mgmt_addr),
|
||||||
|
.cfg_mgmt_write(cfg_mgmt_write),
|
||||||
|
.cfg_mgmt_write_data(cfg_mgmt_write_data),
|
||||||
|
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
|
||||||
|
.cfg_mgmt_read(cfg_mgmt_read),
|
||||||
|
.cfg_mgmt_read_data(cfg_mgmt_read_data),
|
||||||
|
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
|
||||||
|
|
||||||
|
.cfg_fc_ph(cfg_fc_ph),
|
||||||
|
.cfg_fc_pd(cfg_fc_pd),
|
||||||
|
.cfg_fc_nph(cfg_fc_nph),
|
||||||
|
.cfg_fc_npd(cfg_fc_npd),
|
||||||
|
.cfg_fc_cplh(cfg_fc_cplh),
|
||||||
|
.cfg_fc_cpld(cfg_fc_cpld),
|
||||||
|
.cfg_fc_sel(cfg_fc_sel),
|
||||||
|
|
||||||
|
.cfg_ext_read_received(cfg_ext_read_received),
|
||||||
|
.cfg_ext_write_received(cfg_ext_write_received),
|
||||||
|
.cfg_ext_register_number(cfg_ext_register_number),
|
||||||
|
.cfg_ext_function_number(cfg_ext_function_number),
|
||||||
|
.cfg_ext_write_data(cfg_ext_write_data),
|
||||||
|
.cfg_ext_write_byte_enable(cfg_ext_write_byte_enable),
|
||||||
|
.cfg_ext_read_data(cfg_ext_read_data),
|
||||||
|
.cfg_ext_read_data_valid(cfg_ext_read_data_valid),
|
||||||
|
|
||||||
|
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||||
|
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||||
|
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||||
|
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||||
|
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||||
|
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||||
|
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||||
|
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||||
|
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||||
|
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||||
|
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||||
|
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||||
|
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||||
|
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||||
|
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||||
|
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||||
|
|
||||||
|
/*
|
||||||
|
* QSPI flash
|
||||||
|
*/
|
||||||
|
.fpga_boot(fpga_boot),
|
||||||
|
.flash_dq_i(flash_dq_i),
|
||||||
|
.flash_dq_o(flash_dq_o),
|
||||||
|
.flash_dq_oe(flash_dq_oe),
|
||||||
|
.flash_addr(flash_addr),
|
||||||
|
.flash_region(flash_region),
|
||||||
|
.flash_region_oe(flash_region_oe),
|
||||||
|
.flash_ce_n(flash_ce_n),
|
||||||
|
.flash_oe_n(flash_oe_n),
|
||||||
|
.flash_we_n(flash_we_n),
|
||||||
|
.flash_adv_n(flash_adv_n)
|
||||||
|
);
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
`resetall
|
||||||
Reference in New Issue
Block a user