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ptp: Add PTP period output module and testbench

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-02-13 17:06:46 -08:00
parent d1578513c8
commit 38a150b87a
3 changed files with 532 additions and 0 deletions
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54
tb/ptp/taxi_ptp_perout/Makefile Normal file
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# SPDX-License-Identifier: CERN-OHL-S-2.0
#
# Copyright (c) 2020-2025 FPGA Ninja, LLC
#
# Authors:
# - Alex Forencich
TOPLEVEL_LANG = verilog
SIM ?= verilator
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
DUT = taxi_ptp_perout
COCOTB_TEST_MODULES = test_$(DUT)
COCOTB_TOPLEVEL = $(DUT)
MODULE = $(COCOTB_TEST_MODULES)
TOPLEVEL = $(COCOTB_TOPLEVEL)
VERILOG_SOURCES += ../../../rtl/ptp/$(DUT).sv
# handle file list files
process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
# module parameters
export PARAM_FNS_EN := "1'b1"
export PARAM_OUT_START_S := 0
export PARAM_OUT_START_NS := 0
export PARAM_OUT_START_FNS := 0
export PARAM_OUT_PERIOD_S := 1
export PARAM_OUT_PERIOD_NS := 0
export PARAM_OUT_PERIOD_FNS := 0
export PARAM_OUT_WIDTH_S := 0
export PARAM_OUT_WIDTH_NS := 1000
export PARAM_OUT_WIDTH_FNS := 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
else ifeq ($(SIM), verilator)
COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
VERILATOR_TRACE = 1
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim

165
tb/ptp/taxi_ptp_perout/test_taxi_ptp_perout.py Normal file
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#!/usr/bin/env python
# SPDX-License-Identifier: CERN-OHL-S-2.0
"""
Copyright (c) 2020-2025 FPGA Ninja, LLC
Authors:
- Alex Forencich
"""
import logging
import os
import cocotb_test.simulator
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer
from cocotbext.eth import PtpClock
class TB:
def __init__(self, dut):
self.dut = dut
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start())
self.ptp_clock = PtpClock(
ts_tod=dut.input_ts_tod,
ts_step=dut.input_ts_tod_step,
clock=dut.clk,
reset=dut.rst,
period_ns=6.4
)
dut.enable.setimmediatevalue(0)
dut.input_start.setimmediatevalue(0)
dut.input_start_valid.setimmediatevalue(0)
dut.input_period.setimmediatevalue(0)
dut.input_period_valid.setimmediatevalue(0)
dut.input_width.setimmediatevalue(0)
dut.input_width_valid.setimmediatevalue(0)
async def reset(self):
self.dut.rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 0
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
@cocotb.test()
async def run_test(dut):
tb = TB(dut)
await tb.reset()
dut.enable.value = 1
await RisingEdge(dut.clk)
dut.input_start.value = 100 << 16
dut.input_start_valid.value = 1
dut.input_period.value = 100 << 16
dut.input_period_valid.value = 1
dut.input_width.value = 50 << 16
dut.input_width_valid.value = 1
await RisingEdge(dut.clk)
dut.input_start_valid.value = 0
dut.input_period_valid.value = 0
dut.input_width_valid.value = 0
await Timer(10000, 'ns')
await RisingEdge(dut.clk)
dut.input_start.value = 0 << 16
dut.input_start_valid.value = 1
dut.input_period.value = 100 << 16
dut.input_period_valid.value = 1
dut.input_width.value = 50 << 16
dut.input_width_valid.value = 1
await RisingEdge(dut.clk)
dut.input_start_valid.value = 0
dut.input_period_valid.value = 0
dut.input_width_valid.value = 0
await Timer(10000, 'ns')
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
# cocotb-test
tests_dir = os.path.abspath(os.path.dirname(__file__))
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
def process_f_files(files):
lst = {}
for f in files:
if f[-2:].lower() == '.f':
with open(f, 'r') as fp:
l = fp.read().split()
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
lst[os.path.basename(f)] = f
else:
lst[os.path.basename(f)] = f
return list(lst.values())
def test_taxi_ptp_perout(request):
dut = "taxi_ptp_perout"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = dut
verilog_sources = [
os.path.join(rtl_dir, "ptp", f"{dut}.sv"),
]
verilog_sources = process_f_files(verilog_sources)
parameters = {}
parameters['FNS_EN'] = "1'b1"
parameters['OUT_START_S'] = 0
parameters['OUT_START_NS'] = 0
parameters['OUT_START_FNS'] = 0x0000
parameters['OUT_PERIOD_S'] = 1
parameters['OUT_PERIOD_NS'] = 0
parameters['OUT_PERIOD_FNS'] = 0x0000
parameters['OUT_WIDTH_S'] = 0
parameters['OUT_WIDTH_NS'] = 1000
parameters['OUT_WIDTH_FNS'] = 0x0000
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
simulator="verilator",
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)