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pcie: Clean up array init

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-03-08 14:42:31 -07:00
parent bb278958b2
commit 3ac7484e16
2 changed files with 4 additions and 22 deletions
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13
src/pcie/rtl/taxi_pcie_msix_apb.sv
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@@ -139,11 +139,11 @@ logic msix_mask_reg = 1'b0;
// MSI-X table // MSI-X table
(* ramstyle = "no_rw_check, mlab" *) (* ramstyle = "no_rw_check, mlab" *)
logic [63:0] tbl_mem[2**TBL_ADDR_W]; logic [63:0] tbl_mem[2**TBL_ADDR_W] = '{default: '0};
// MSI-X PBA // MSI-X PBA
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
logic [63:0] pba_mem[2**PBA_ADDR_W]; logic [63:0] pba_mem[2**PBA_ADDR_W] = '{default: '0};
logic tbl_rd_data_valid_reg = 1'b0, tbl_rd_data_valid_next; logic tbl_rd_data_valid_reg = 1'b0, tbl_rd_data_valid_next;
logic pba_rd_data_valid_reg = 1'b0, pba_rd_data_valid_next; logic pba_rd_data_valid_reg = 1'b0, pba_rd_data_valid_next;
@@ -176,15 +176,6 @@ assign tx_wr_req_tlp.valid = tx_wr_req_tlp_valid_reg;
assign tx_wr_req_tlp.sop = 1'b1; assign tx_wr_req_tlp.sop = 1'b1;
assign tx_wr_req_tlp.eop = 1'b1; assign tx_wr_req_tlp.eop = 1'b1;
initial begin
for (integer i = 0; i < 2**TBL_ADDR_W; i = i + 1) begin
tbl_mem[i] = '0;
end
for (integer i = 0; i < 2**PBA_ADDR_W; i = i + 1) begin
pba_mem[i] = '0;
end
end
always_comb begin always_comb begin
state_next = STATE_IDLE; state_next = STATE_IDLE;

13
src/pcie/rtl/taxi_pcie_msix_axil.sv
View File

@@ -149,11 +149,11 @@ logic msix_mask_reg = 1'b0;
// MSI-X table // MSI-X table
(* ramstyle = "no_rw_check, mlab" *) (* ramstyle = "no_rw_check, mlab" *)
logic [63:0] tbl_mem[2**TBL_ADDR_W]; logic [63:0] tbl_mem[2**TBL_ADDR_W] = '{default: '0};
// MSI-X PBA // MSI-X PBA
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
logic [63:0] pba_mem[2**PBA_ADDR_W]; logic [63:0] pba_mem[2**PBA_ADDR_W] = '{default: '0};
logic tbl_rd_data_valid_reg = 1'b0, tbl_rd_data_valid_next; logic tbl_rd_data_valid_reg = 1'b0, tbl_rd_data_valid_next;
logic pba_rd_data_valid_reg = 1'b0, pba_rd_data_valid_next; logic pba_rd_data_valid_reg = 1'b0, pba_rd_data_valid_next;
@@ -194,15 +194,6 @@ assign tx_wr_req_tlp.valid = tx_wr_req_tlp_valid_reg;
assign tx_wr_req_tlp.sop = 1'b1; assign tx_wr_req_tlp.sop = 1'b1;
assign tx_wr_req_tlp.eop = 1'b1; assign tx_wr_req_tlp.eop = 1'b1;
initial begin
for (integer i = 0; i < 2**TBL_ADDR_W; i = i + 1) begin
tbl_mem[i] = '0;
end
for (integer i = 0; i < 2**PBA_ADDR_W; i = i + 1) begin
pba_mem[i] = '0;
end
end
always_comb begin always_comb begin
state_next = STATE_IDLE; state_next = STATE_IDLE;