bslathi19/taxi
1
0
Fork 0
mirror of https://github.com/fpganinja/taxi.git synced 2025-12-07 16:28:40 -08:00
Code Issues Packages Projects Releases Wiki Activity

eth: Ensure header pointer is wide enough to clear the entire header before halting

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2025-04-26 19:31:51 -07:00
parent be7016991a
commit 3dc7e4821d
6 changed files with 20 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
rtl/eth/taxi_axis_baser_rx_64.sv
View File

@@ -179,7 +179,7 @@ logic input_start_d1 = 1'b0;
logic frame_oversize_reg = 1'b0, frame_oversize_next;
logic pre_ok_reg = 1'b0, pre_ok_next;
logic [0:0] hdr_ptr_reg = '0, hdr_ptr_next;
logic [1:0] hdr_ptr_reg = '0, hdr_ptr_next;
logic is_mcast_reg = 1'b0, is_mcast_next;
logic is_bcast_reg = 1'b0, is_bcast_next;
logic is_8021q_reg = 1'b0, is_8021q_next;
@@ -368,11 +368,11 @@ always_comb begin
end
case (hdr_ptr_reg)
1'd0: begin
2'd0: begin
is_mcast_next = input_data_d1[0];
is_bcast_next = &input_data_d1[47:0];
end
1'd1: is_8021q_next = {input_data_d1[39:32], input_data_d1[47:40]} == 16'h8100;
2'd1: is_8021q_next = {input_data_d1[39:32], input_data_d1[47:40]} == 16'h8100;
default: begin
// do nothing
end

6
rtl/eth/taxi_axis_baser_tx_64.sv
View File

@@ -189,7 +189,7 @@ logic frame_reg = 1'b0, frame_next;
logic frame_error_reg = 1'b0, frame_error_next;
logic frame_oversize_reg = 1'b0, frame_oversize_next;
logic [MIN_LEN_W-1:0] frame_min_count_reg = '0, frame_min_count_next;
logic [0:0] hdr_ptr_reg = '0, hdr_ptr_next;
logic [1:0] hdr_ptr_reg = '0, hdr_ptr_next;
logic is_mcast_reg = 1'b0, is_mcast_next;
logic is_bcast_reg = 1'b0, is_bcast_next;
logic is_8021q_reg = 1'b0, is_8021q_next;
@@ -440,11 +440,11 @@ always_comb begin
end
case (hdr_ptr_reg)
1'd0: begin
2'd0: begin
is_mcast_next = s_tdata_reg[0];
is_bcast_next = &s_tdata_reg[47:0];
end
1'd1: is_8021q_next = {s_tdata_reg[39:32], s_tdata_reg[47:40]} == 16'h8100;
2'd1: is_8021q_next = {s_tdata_reg[39:32], s_tdata_reg[47:40]} == 16'h8100;
default: begin
// do nothing
end

8
rtl/eth/taxi_axis_xgmii_rx_32.sv
View File

@@ -123,7 +123,7 @@ logic xgmii_start_d2 = 1'b0;
logic frame_oversize_reg = 1'b0, frame_oversize_next;
logic pre_ok_reg = 1'b0, pre_ok_next;
logic [1:0] hdr_ptr_reg = '0, hdr_ptr_next;
logic [2:0] hdr_ptr_reg = '0, hdr_ptr_next;
logic is_mcast_reg = 1'b0, is_mcast_next;
logic is_bcast_reg = 1'b0, is_bcast_next;
logic is_8021q_reg = 1'b0, is_8021q_next;
@@ -279,12 +279,12 @@ always_comb begin
end
case (hdr_ptr_reg)
2'd0: begin
3'd0: begin
is_mcast_next = xgmii_rxd_d2[0];
is_bcast_next = &xgmii_rxd_d2;
end
2'd1: is_bcast_next = is_bcast_reg && &xgmii_rxd_d2[15:0];
2'd3: is_8021q_next = {xgmii_rxd_d2[7:0], xgmii_rxd_d2[15:8]} == 16'h8100;
3'd1: is_bcast_next = is_bcast_reg && &xgmii_rxd_d2[15:0];
3'd3: is_8021q_next = {xgmii_rxd_d2[7:0], xgmii_rxd_d2[15:8]} == 16'h8100;
default: begin
// do nothing
end

6
rtl/eth/taxi_axis_xgmii_rx_64.sv
View File

@@ -127,7 +127,7 @@ logic xgmii_start_d1 = 1'b0;
logic frame_oversize_reg = 1'b0, frame_oversize_next;
logic pre_ok_reg = 1'b0, pre_ok_next;
logic [0:0] hdr_ptr_reg = '0, hdr_ptr_next;
logic [1:0] hdr_ptr_reg = '0, hdr_ptr_next;
logic is_mcast_reg = 1'b0, is_mcast_next;
logic is_bcast_reg = 1'b0, is_bcast_next;
logic is_8021q_reg = 1'b0, is_8021q_next;
@@ -298,11 +298,11 @@ always_comb begin
end
case (hdr_ptr_reg)
1'd0: begin
2'd0: begin
is_mcast_next = xgmii_rxd_d1[0];
is_bcast_next = &xgmii_rxd_d1[47:0];
end
1'd1: is_8021q_next = {xgmii_rxd_d1[39:32], xgmii_rxd_d1[47:40]} == 16'h8100;
2'd1: is_8021q_next = {xgmii_rxd_d1[39:32], xgmii_rxd_d1[47:40]} == 16'h8100;
default: begin
// do nothing
end

8
rtl/eth/taxi_axis_xgmii_tx_32.sv
View File

@@ -135,7 +135,7 @@ logic frame_reg = 1'b0, frame_next;
logic frame_error_reg = 1'b0, frame_error_next;
logic frame_oversize_reg = 1'b0, frame_oversize_next;
logic [MIN_LEN_W-1:0] frame_min_count_reg = '0, frame_min_count_next;
logic [1:0] hdr_ptr_reg = '0, hdr_ptr_next;
logic [2:0] hdr_ptr_reg = '0, hdr_ptr_next;
logic is_mcast_reg = 1'b0, is_mcast_next;
logic is_bcast_reg = 1'b0, is_bcast_next;
logic is_8021q_reg = 1'b0, is_8021q_next;
@@ -365,12 +365,12 @@ always_comb begin
end
case (hdr_ptr_reg)
2'd0: begin
3'd0: begin
is_mcast_next = s_tdata_reg[0];
is_bcast_next = &s_tdata_reg;
end
2'd1: is_bcast_next = is_bcast_reg && &s_tdata_reg[15:0];
2'd3: is_8021q_next = {s_tdata_reg[7:0], s_tdata_reg[15:8]} == 16'h8100;
3'd1: is_bcast_next = is_bcast_reg && &s_tdata_reg[15:0];
3'd3: is_8021q_next = {s_tdata_reg[7:0], s_tdata_reg[15:8]} == 16'h8100;
default: begin
// do nothing
end

6
rtl/eth/taxi_axis_xgmii_tx_64.sv
View File

@@ -137,7 +137,7 @@ logic frame_reg = 1'b0, frame_next;
logic frame_error_reg = 1'b0, frame_error_next;
logic frame_oversize_reg = 1'b0, frame_oversize_next;
logic [MIN_LEN_W-1:0] frame_min_count_reg = '0, frame_min_count_next;
logic [0:0] hdr_ptr_reg = '0, hdr_ptr_next;
logic [1:0] hdr_ptr_reg = '0, hdr_ptr_next;
logic is_mcast_reg = 1'b0, is_mcast_next;
logic is_bcast_reg = 1'b0, is_bcast_next;
logic is_8021q_reg = 1'b0, is_8021q_next;
@@ -386,11 +386,11 @@ always_comb begin
end
case (hdr_ptr_reg)
1'd0: begin
2'd0: begin
is_mcast_next = s_tdata_reg[0];
is_bcast_next = &s_tdata_reg[47:0];
end
1'd1: is_8021q_next = {s_tdata_reg[39:32], s_tdata_reg[47:40]} == 16'h8100;
2'd1: is_8021q_next = {s_tdata_reg[39:32], s_tdata_reg[47:40]} == 16'h8100;
default: begin
// do nothing
end