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axi: When tying AXI interfaces, permit narrowing the address bus

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
2026-03-15 16:01:53 -07:00
parent 7a9e9f3370
commit 446dc19fc6
4 changed files with 16 additions and 4 deletions
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5
src/axi/rtl/taxi_axi_tie_rd.sv
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@@ -39,6 +39,9 @@ localparam logic RUSER_EN = s_axi_rd.RUSER_EN && m_axi_rd.RUSER_EN;
localparam RUSER_W = s_axi_rd.RUSER_W;
// check configuration
if (m_axi_rd.ADDR_W > ADDR_W)
$fatal(0, "Error: Output ADDR_W is wider than input ADDR_W, cannot access entire address space (instance %m)");
if (m_axi_rd.DATA_W != DATA_W)
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
@@ -46,7 +49,7 @@ if (m_axi_rd.STRB_W != STRB_W)
$fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
assign m_axi_rd.arid = s_axi_rd.arid;
assign m_axi_rd.araddr = s_axi_rd.araddr;
assign m_axi_rd.araddr = m_axi_wr.ADDR_W'(s_axi_rd.araddr);
assign m_axi_rd.arlen = s_axi_rd.arlen;
assign m_axi_rd.arsize = s_axi_rd.arsize;
assign m_axi_rd.arburst = s_axi_rd.arburst;

5
src/axi/rtl/taxi_axi_tie_wr.sv
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@@ -41,6 +41,9 @@ localparam logic BUSER_EN = s_axi_wr.BUSER_EN && m_axi_wr.BUSER_EN;
localparam BUSER_W = s_axi_wr.BUSER_W;
// check configuration
if (m_axi_wr.ADDR_W > ADDR_W)
$fatal(0, "Error: Output ADDR_W is wider than input ADDR_W, cannot access entire address space (instance %m)");
if (m_axi_wr.DATA_W != DATA_W)
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
@@ -49,7 +52,7 @@ if (m_axi_wr.STRB_W != STRB_W)
// bypass AW channel
assign m_axi_wr.awid = s_axi_wr.awid;
assign m_axi_wr.awaddr = s_axi_wr.awaddr;
assign m_axi_wr.awaddr = m_axi_wr.ADDR_W'(s_axi_wr.awaddr);
assign m_axi_wr.awlen = s_axi_wr.awlen;
assign m_axi_wr.awsize = s_axi_wr.awsize;
assign m_axi_wr.awburst = s_axi_wr.awburst;

5
src/axi/rtl/taxi_axil_tie_rd.sv
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@@ -38,13 +38,16 @@ localparam logic RUSER_EN = s_axil_rd.RUSER_EN && m_axil_rd.RUSER_EN;
localparam RUSER_W = s_axil_rd.RUSER_W;
// check configuration
if (m_axil_rd.ADDR_W > ADDR_W)
$fatal(0, "Error: Output ADDR_W is wider than input ADDR_W, cannot access entire address space (instance %m)");
if (m_axil_rd.DATA_W != DATA_W)
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
if (m_axil_rd.STRB_W != STRB_W)
$fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
assign m_axil_rd.araddr = s_axil_rd.araddr;
assign m_axil_rd.araddr = m_axil_rd.ADDR_W'(s_axil_rd.araddr);
assign m_axil_rd.arprot = s_axil_rd.arprot;
assign m_axil_rd.aruser = ARUSER_EN ? s_axil_rd.aruser : '0;
assign m_axil_rd.arvalid = s_axil_rd.arvalid;

5
src/axi/rtl/taxi_axil_tie_wr.sv
View File

@@ -40,6 +40,9 @@ localparam logic BUSER_EN = s_axil_wr.BUSER_EN && m_axil_wr.BUSER_EN;
localparam BUSER_W = s_axil_wr.BUSER_W;
// check configuration
if (m_axil_wr.ADDR_W > ADDR_W)
$fatal(0, "Error: Output ADDR_W is wider than input ADDR_W, cannot access entire address space (instance %m)");
if (m_axil_wr.DATA_W != DATA_W)
$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
@@ -47,7 +50,7 @@ if (m_axil_wr.STRB_W != STRB_W)
$fatal(0, "Error: Interface STRB_W parameter mismatch (instance %m)");
// bypass AW channel
assign m_axil_wr.awaddr = s_axil_wr.awaddr;
assign m_axil_wr.awaddr = m_axil_wr.ADDR_W'(s_axil_wr.awaddr);
assign m_axil_wr.awprot = s_axil_wr.awprot;
assign m_axil_wr.awuser = AWUSER_EN ? s_axil_wr.awuser : '0;
assign m_axil_wr.awvalid = s_axil_wr.awvalid;