lss: Add I2C master module and testbench

Signed-off-by: Alex Forencich <alex@alexforencich.com>

tb/lss/taxi_i2c_master/Makefile

@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+#
+# Copyright (c) 2020-2025 FPGA Ninja, LLC
+#
+# Authors:
+# - Alex Forencich
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= verilator
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ns
+
+DUT      = taxi_i2c_master
+COCOTB_TEST_MODULES = test_$(DUT)
+COCOTB_TOPLEVEL     = test_$(DUT)
+MODULE   = $(COCOTB_TEST_MODULES)
+TOPLEVEL = $(COCOTB_TOPLEVEL)
+VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
+VERILOG_SOURCES += ../../../rtl/lss/$(DUT).sv
+VERILOG_SOURCES += ../../../rtl/axis/taxi_axis_if.sv
+
+# handle file list files
+process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
+process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
+uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
+VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
+
+# module parameters
+# export PARAM_DEFAULT_PRESCALE := 1
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+		VERILATOR_TRACE = 1
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim

tb/lss/taxi_i2c_master/test_taxi_i2c_master.py

@@ -0,0 +1,189 @@
+#!/usr/bin/env python
+# SPDX-License-Identifier: CERN-OHL-S-2.0
+"""
+
+Copyright (c) 2020-2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+"""
+
+import logging
+import os
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import RisingEdge, FallingEdge
+from cocotb.regression import TestFactory
+
+from cocotbext.axi import AxiStreamSource, AxiStreamSink, AxiStreamBus
+from cocotbext.i2c import I2cMemory
+
+
+CMD_START        = 1 << 7
+CMD_READ         = 1 << 8
+CMD_WRITE        = 1 << 9
+CMD_WRITE_MULTI  = 1 << 10
+CMD_STOP         = 1 << 11
+
+
+class TB:
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = logging.getLogger("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        cocotb.fork(Clock(dut.clk, 8, units="ns").start())
+
+        self.cmd_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_cmd), dut.clk, dut.rst)
+
+        self.data_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_data), dut.clk, dut.rst)
+        self.data_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_data), dut.clk, dut.rst)
+
+        self.i2c_memory = I2cMemory(sda=dut.sda_o, sda_o=dut.sda_i,
+            scl=dut.scl_o, scl_o=dut.scl_i, addr=0x50, size=1024)
+
+        dut.prescale.setimmediatevalue(2)
+        dut.stop_on_idle.setimmediatevalue(0)
+
+    async def reset(self):
+        self.dut.rst.setimmediatevalue(0)
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 1
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+        self.dut.rst.value = 0
+        await RisingEdge(self.dut.clk)
+        await RisingEdge(self.dut.clk)
+
+    async def i2c_write_data(self, addr, data, start=0, stop=0):
+        cmd = CMD_WRITE_MULTI | addr
+        if start:
+            cmd |= CMD_START
+        if stop:
+            cmd |= CMD_STOP
+        await self.cmd_source.send([cmd])
+        await self.data_source.send(data)
+        await self.data_source.wait()
+        await self.i2c_wait()
+
+    async def i2c_read_data(self, addr, count, start=0, stop=0):
+        for k in range(count):
+            cmd = CMD_READ | addr
+            if start and k == 0:
+                cmd |= CMD_START
+            if stop and k == count-1:
+                cmd |= CMD_STOP
+            await self.cmd_source.send([cmd])
+        return (await self.data_sink.recv()).tdata
+
+    async def i2c_wait(self):
+        if self.dut.busy.value.integer:
+            await FallingEdge(self.dut.busy)
+
+    async def i2c_wait_bus_idle(self):
+        if self.dut.bus_active.value.integer:
+            await FallingEdge(self.dut.bus_active)
+
+
+async def run_test(dut, payload_lengths=None, payload_data=None):
+
+    tb = TB(dut)
+
+    await tb.reset()
+
+    tb.log.info("Test write")
+
+    test_data = b'\x11\x22\x33\x44'
+
+    await tb.i2c_write_data(0x50, b'\x00\x04'+test_data, stop=1)
+    await tb.i2c_wait_bus_idle()
+
+    data = tb.i2c_memory.read_mem(4, 4)
+
+    tb.log.info("Read data: %s", data)
+
+    assert data == test_data
+
+    # assert not missed ack
+
+    tb.log.info("Test read")
+
+    await tb.i2c_write_data(0x50, b'\x00\x04')
+    read_data = await tb.i2c_read_data(0x50, 4, start=1, stop=1)
+
+    tb.log.info("Read data: %s", read_data)
+
+    assert read_data == test_data
+
+    # assert not missed ack
+
+    tb.log.info("Test write to nonexistent device")
+
+    await tb.i2c_write_data(0x55, b'\x00\x04'+b'\xde\xad\xbe\xef', stop=1)
+    await tb.i2c_wait_bus_idle()
+
+    # assert missed ack
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+if cocotb.SIM_NAME:
+
+    factory = TestFactory(run_test)
+    factory.generate_tests()
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', '..', 'rtl'))
+
+
+def process_f_files(files):
+    lst = {}
+    for f in files:
+        if f[-2:].lower() == '.f':
+            with open(f, 'r') as fp:
+                l = fp.read().split()
+            for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
+                lst[os.path.basename(f)] = f
+        else:
+            lst[os.path.basename(f)] = f
+    return list(lst.values())
+
+
+def test_taxi_i2c_master(request):
+    dut = "taxi_i2c_master"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = module
+
+    verilog_sources = [
+        os.path.join(tests_dir, f"{toplevel}.sv"),
+        os.path.join(rtl_dir, "lss", f"{dut}.sv"),
+        os.path.join(rtl_dir, "axis", "taxi_axis_if.sv"),
+    ]
+
+    parameters = {}
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        simulator="verilator",
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

tb/lss/taxi_i2c_master/test_taxi_i2c_master.sv

@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: CERN-OHL-S-2.0
+/*
+
+Copyright (c) 2025 FPGA Ninja, LLC
+
+Authors:
+- Alex Forencich
+
+*/
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * I2C master testbench
+ */
+module test_taxi_i2c_master
+();
+
+logic clk;
+logic rst;
+
+taxi_axis_if #(.DATA_W(12), .KEEP_W(1)) s_axis_cmd();
+taxi_axis_if #(.DATA_W(8)) s_axis_data();
+taxi_axis_if #(.DATA_W(8)) m_axis_data();
+
+logic scl_i;
+logic scl_o;
+logic scl_t;
+logic sda_i;
+logic sda_o;
+logic sda_t;
+
+logic busy;
+logic bus_control;
+logic bus_active;
+logic missed_ack;
+
+logic [15:0] prescale;
+logic stop_on_idle;
+
+taxi_i2c_master
+uut (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * Host interface
+     */
+    .s_axis_cmd(s_axis_cmd),
+    .s_axis_data(s_axis_data),
+    .m_axis_data(m_axis_data),
+
+    /*
+     * I2C interface
+     */
+    .scl_i(scl_i),
+    .scl_o(scl_o),
+    .scl_t(scl_t),
+    .sda_i(sda_i),
+    .sda_o(sda_o),
+    .sda_t(sda_t),
+
+    /*
+     * Status
+     */
+    .busy(busy),
+    .bus_control(bus_control),
+    .bus_active(bus_active),
+    .missed_ack(missed_ack),
+
+    /*
+     * Configuration
+     */
+    .prescale(prescale),
+    .stop_on_idle(stop_on_idle)
+);
+
+endmodule
+
+`resetall