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zircon: Add length and checksum computation module and testbench
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
202
src/zircon/rtl/zircon_ip_len_cksum.sv
Normal file
202
src/zircon/rtl/zircon_ip_len_cksum.sv
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@@ -0,0 +1,202 @@
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// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Zircon IP stack - Length and checksum computation
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*/
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module zircon_ip_len_cksum #
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(
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parameter START_OFFSET = 14
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* Packet passthrough
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*/
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taxi_axis_if.snk s_axis_pkt,
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taxi_axis_if.src m_axis_pkt,
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/*
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* Packet metadata output
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*/
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taxi_axis_if.src m_axis_meta
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);
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localparam DATA_W = s_axis_pkt.DATA_W;
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localparam KEEP_W = s_axis_pkt.KEEP_W;
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localparam META_W = m_axis_meta.DATA_W;
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localparam ID_W = m_axis_meta.ID_W;
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localparam ID_EN = s_axis_pkt.ID_EN && m_axis_meta.ID_EN;
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localparam DEST_W = m_axis_meta.DEST_W;
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localparam DEST_EN = s_axis_pkt.DEST_EN && m_axis_meta.DEST_EN;
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localparam USER_W = m_axis_meta.USER_W;
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localparam USER_EN = s_axis_pkt.USER_EN && m_axis_meta.USER_EN;
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parameter LEVELS = $clog2(DATA_W/8);
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parameter OFFSET_W = START_OFFSET/KEEP_W > 1 ? $clog2(START_OFFSET/KEEP_W) : 1;
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// check configuration
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if (KEEP_W * 8 != DATA_W)
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$fatal(0, "Error: Interface requires byte (8-bit) granularity (instance %m)");
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if (META_W != 32)
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$fatal(0, "Error: Interface width must be 32 (instance %m)");
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if (m_axis_meta.KEEP_W * 8 != META_W)
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$fatal(0, "Error: Interface requires byte (8-bit) granularity (instance %m)");
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logic [OFFSET_W-1:0] offset_reg = OFFSET_W'(START_OFFSET/KEEP_W);
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logic [KEEP_W-1:0] mask_reg = {KEEP_W{1'b1}} << START_OFFSET;
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logic [DATA_W-1:0] sum_reg[LEVELS-2:0];
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logic [(LEVELS-1)*4-1:0] len_reg[LEVELS-2:0];
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logic [ID_W-1:0] id_reg[LEVELS-2:0];
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logic [DEST_W-1:0] dest_reg[LEVELS-2:0];
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logic [USER_W-1:0] user_reg[LEVELS-2:0];
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logic [LEVELS-2:0] sum_valid_reg = '0;
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logic [LEVELS-2:0] sum_last_reg = '0;
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logic [16+LEVELS-1:0] sum_acc_temp;
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logic [15:0] sum_acc_reg = '0;
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logic [15:0] len_acc_reg = '0;
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logic [15:0] m_axis_meta_len_reg = '0;
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logic [15:0] m_axis_meta_csum_reg = '0;
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logic m_axis_meta_valid_reg = 1'b0;
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logic [ID_W-1:0] m_axis_meta_id_reg = '0;
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logic [DEST_W-1:0] m_axis_meta_dest_reg = '0;
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logic [USER_W-1:0] m_axis_meta_user_reg = '0;
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assign m_axis_pkt.tdata = s_axis_pkt.tdata;
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assign m_axis_pkt.tkeep = s_axis_pkt.tkeep;
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assign m_axis_pkt.tstrb = s_axis_pkt.tstrb;
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assign m_axis_pkt.tid = s_axis_pkt.tid;
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assign m_axis_pkt.tdest = s_axis_pkt.tdest;
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assign m_axis_pkt.tuser = s_axis_pkt.tuser;
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assign m_axis_pkt.tlast = s_axis_pkt.tlast;
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assign m_axis_pkt.tvalid = s_axis_pkt.tvalid;
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assign s_axis_pkt.tready = m_axis_pkt.tready;
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assign m_axis_meta.tdata = {m_axis_meta_csum_reg, m_axis_meta_len_reg};
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assign m_axis_meta.tkeep = '1;
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assign m_axis_meta.tstrb = m_axis_meta.tkeep;
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assign m_axis_meta.tid = ID_EN ? m_axis_meta_id_reg : '0;
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assign m_axis_meta.tdest = DEST_EN ? m_axis_meta_dest_reg : '0;
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assign m_axis_meta.tuser = USER_EN ? m_axis_meta_user_reg : '0;
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assign m_axis_meta.tlast = 1'b1;
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assign m_axis_meta.tvalid = m_axis_meta_valid_reg;
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// Mask input data
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wire [DATA_W-1:0] pkt_data_masked;
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for (genvar j = 0; j < KEEP_W; j = j + 1) begin
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assign pkt_data_masked[j*8 +: 8] = (s_axis_pkt.tkeep[j] && mask_reg[j]) ? s_axis_pkt.tdata[j*8 +: 8] : 8'd0;
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end
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always_ff @(posedge clk) begin
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sum_valid_reg[0] <= 1'b0;
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if (s_axis_pkt.tvalid && s_axis_pkt.tready) begin
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for (integer i = 0; i < DATA_W/8/4; i = i + 1) begin
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sum_reg[0][i*17 +: 17] <= {pkt_data_masked[(4*i+0)*8 +: 8], pkt_data_masked[(4*i+1)*8 +: 8]} + {pkt_data_masked[(4*i+2)*8 +: 8], pkt_data_masked[(4*i+3)*8 +: 8]};
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len_reg[0][i*3 +: 3] <= 3'(s_axis_pkt.tkeep[(4*i+0)]) + 3'(s_axis_pkt.tkeep[(4*i+1)]) + 3'(s_axis_pkt.tkeep[(4*i+2)]) + 3'(s_axis_pkt.tkeep[(4*i+3)]);
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end
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sum_valid_reg[0] <= 1'b1;
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sum_last_reg[0] <= s_axis_pkt.tlast;
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id_reg[0] <= ID_W'(s_axis_pkt.tid);
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dest_reg[0] <= DEST_W'(s_axis_pkt.tdest);
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user_reg[0] <= USER_W'(s_axis_pkt.tuser);
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if (s_axis_pkt.tlast) begin
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offset_reg <= OFFSET_W'(START_OFFSET/KEEP_W);
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mask_reg <= {KEEP_W{1'b1}} << START_OFFSET;
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end else if (START_OFFSET < KEEP_W || offset_reg == 0) begin
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mask_reg <= {KEEP_W{1'b1}};
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end else begin
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offset_reg <= offset_reg - 1;
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if (offset_reg == 1) begin
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mask_reg <= {KEEP_W{1'b1}} << (START_OFFSET%KEEP_W);
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end else begin
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mask_reg <= {KEEP_W{1'b0}};
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end
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end
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end
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if (rst) begin
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offset_reg <= OFFSET_W'(START_OFFSET/KEEP_W);
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mask_reg <= {KEEP_W{1'b1}} << START_OFFSET;
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sum_valid_reg[0] <= 1'b0;
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end
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end
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for (genvar l = 1; l < LEVELS-1; l = l + 1) begin
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always_ff @(posedge clk) begin
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sum_valid_reg[l] <= 1'b0;
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if (sum_valid_reg[l-1]) begin
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for (integer i = 0; i < DATA_W/8/4/2**l; i = i + 1) begin
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sum_reg[l][i*(17+l) +: (17+l)] <= sum_reg[l-1][(i*2+0)*(17+l-1) +: (17+l-1)] + sum_reg[l-1][(i*2+1)*(17+l-1) +: (17+l-1)];
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len_reg[l][i*(3+l) +: (3+l)] <= len_reg[l-1][(i*2+0)*(3+l-1) +: (3+l-1)] + len_reg[l-1][(i*2+1)*(3+l-1) +: (3+l-1)];
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end
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sum_valid_reg[l] <= 1'b1;
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sum_last_reg[l] <= sum_last_reg[l-1];
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id_reg[l] <= id_reg[l-1];
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dest_reg[l] <= dest_reg[l-1];
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user_reg[l] <= user_reg[l-1];
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end
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if (rst) begin
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sum_valid_reg[l] <= 1'b0;
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end
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end
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end
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always_ff @(posedge clk) begin
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m_axis_meta_valid_reg <= 1'b0;
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sum_acc_temp = sum_reg[LEVELS-2][16+LEVELS-1-1:0] + (16+LEVELS)'(sum_acc_reg);
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sum_acc_temp = (16+LEVELS)'(sum_acc_temp[15:0] + 16'(sum_acc_temp >> 16));
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sum_acc_temp = (16+LEVELS)'(sum_acc_temp[15:0] + 16'(sum_acc_temp[16]));
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m_axis_meta_len_reg <= len_acc_reg + 16'(len_reg[LEVELS-2][3+LEVELS-1-1:0]);
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m_axis_meta_csum_reg <= sum_acc_temp[15:0];
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m_axis_meta_id_reg <= id_reg[LEVELS-2];
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m_axis_meta_dest_reg <= dest_reg[LEVELS-2];
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m_axis_meta_user_reg <= user_reg[LEVELS-2];
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if (sum_valid_reg[LEVELS-2]) begin
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if (sum_last_reg[LEVELS-2]) begin
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m_axis_meta_valid_reg <= 1'b1;
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sum_acc_reg <= '0;
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len_acc_reg <= '0;
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end else begin
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sum_acc_reg <= sum_acc_temp[15:0];
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len_acc_reg <= len_acc_reg + 16'(len_reg[LEVELS-2][3+LEVELS-1-1:0]);
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end
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end
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if (rst) begin
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m_axis_meta_valid_reg <= 1'b0;
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sum_acc_reg <= '0;
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end
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end
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endmodule
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`resetall
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53
src/zircon/tb/zircon_ip_len_cksum/Makefile
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53
src/zircon/tb/zircon_ip_len_cksum/Makefile
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@@ -0,0 +1,53 @@
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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#
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# Copyright (c) 2025 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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TOPLEVEL_LANG = verilog
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SIM ?= verilator
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WAVES ?= 0
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COCOTB_HDL_TIMEUNIT = 1ns
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COCOTB_HDL_TIMEPRECISION = 1ps
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RTL_DIR = ../../rtl
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LIB_DIR = ../../lib
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TAXI_SRC_DIR = $(LIB_DIR)/taxi/src
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DUT = zircon_ip_len_cksum
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COCOTB_TEST_MODULES = test_$(DUT)
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COCOTB_TOPLEVEL = test_$(DUT)
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MODULE = $(COCOTB_TEST_MODULES)
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TOPLEVEL = $(COCOTB_TOPLEVEL)
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VERILOG_SOURCES += $(COCOTB_TOPLEVEL).sv
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VERILOG_SOURCES += $(RTL_DIR)/$(DUT).sv
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VERILOG_SOURCES += $(TAXI_SRC_DIR)/axis/rtl/taxi_axis_if.sv
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# handle file list files
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process_f_file = $(call process_f_files,$(addprefix $(dir $1),$(shell cat $1)))
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process_f_files = $(foreach f,$1,$(if $(filter %.f,$f),$(call process_f_file,$f),$f))
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uniq_base = $(if $1,$(call uniq_base,$(foreach f,$1,$(if $(filter-out $(notdir $(lastword $1)),$(notdir $f)),$f,))) $(lastword $1))
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VERILOG_SOURCES := $(call uniq_base,$(call process_f_files,$(VERILOG_SOURCES)))
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# module parameters
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export PARAM_DATA_W := 32
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export PARAM_META_W := 32
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export PARAM_START_OFFSET := 14
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-P $(COCOTB_TOPLEVEL).$(subst PARAM_,,$(v))=$($(v)))
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else ifeq ($(SIM), verilator)
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COMPILE_ARGS += $(foreach v,$(filter PARAM_%,$(.VARIABLES)),-G$(subst PARAM_,,$(v))=$($(v)))
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ifeq ($(WAVES), 1)
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COMPILE_ARGS += --trace-fst
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VERILATOR_TRACE = 1
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endif
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endif
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include $(shell cocotb-config --makefiles)/Makefile.sim
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287
src/zircon/tb/zircon_ip_len_cksum/test_zircon_ip_len_cksum.py
Normal file
287
src/zircon/tb/zircon_ip_len_cksum/test_zircon_ip_len_cksum.py
Normal file
@@ -0,0 +1,287 @@
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#!/usr/bin/env python
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# SPDX-License-Identifier: CERN-OHL-S-2.0
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"""
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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"""
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import logging
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import os
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import struct
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import scapy.config
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import scapy.utils
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import scapy.pton_ntop
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from scapy.layers.l2 import Ether, Dot1Q, Dot1AD, ARP
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from scapy.layers.inet import IP, ICMP, UDP, TCP
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from scapy.layers.inet import IPOption_MTU_Probe
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from scapy.layers.inet6 import IPv6, ICMPv6ND_NS
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from scapy.layers.inet6 import IPv6ExtHdrFragment, IPv6ExtHdrHopByHop, RouterAlert
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import cocotb_test.simulator
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import RisingEdge
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from cocotb.regression import TestFactory
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from cocotbext.axi import AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamFrame
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# don't hide ports
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scapy.config.conf.noenum.add(TCP.sport, TCP.dport)
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scapy.config.conf.noenum.add(UDP.sport, UDP.dport)
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class TB:
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def __init__(self, dut):
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self.dut = dut
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self.log = logging.getLogger("cocotb.tb")
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self.log.setLevel(logging.DEBUG)
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cocotb.start_soon(Clock(dut.clk, 3.2, units="ns").start())
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self.pkt_source = AxiStreamSource(AxiStreamBus.from_entity(dut.s_axis_pkt), dut.clk, dut.rst)
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self.pkt_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_pkt), dut.clk, dut.rst)
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self.meta_sink = AxiStreamSink(AxiStreamBus.from_entity(dut.m_axis_meta), dut.clk, dut.rst)
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async def reset(self):
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self.dut.rst.setimmediatevalue(0)
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 1
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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self.dut.rst.value = 0
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await RisingEdge(self.dut.clk)
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await RisingEdge(self.dut.clk)
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async def run_test(dut):
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tb = TB(dut)
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await tb.reset()
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test_pkts = []
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payload = bytearray(range(64))
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ip_id = 0
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l2hdrs = []
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# Ethernet
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eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
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l2hdrs.append(eth)
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# Ethernet with 802.1Q VLAN
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eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
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vlan = Dot1Q(vlan=123)
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l2hdrs.append(eth / vlan)
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# Ethernet with 802.1Q QinQ
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eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
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vlan = Dot1AD(vlan=456)
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l2hdrs.append(eth / vlan)
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# Ethernet with 802.1Q QinQ and VLAN
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eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
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vlan = Dot1AD(vlan=456) / Dot1Q(vlan=123)
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l2hdrs.append(eth / vlan)
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for l2hdr in l2hdrs:
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# Raw ethernet
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test_pkts.append(l2hdr / payload)
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# ARP
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arp = ARP(hwtype=1, ptype=0x0800, hwlen=6, plen=4, op=2,
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hwsrc='5A:51:52:53:54:55', psrc='192.168.1.100',
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hwdst='DA:D1:D2:D3:D4:D5', pdst='192.168.1.101')
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test_pkts.append(l2hdr / arp)
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l3hdrs = []
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# IPv4
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ip = IP(src='10.1.0.1', dst='10.2.0.1', id=ip_id)
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l3hdrs.append(ip)
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# IPv4 (fragmented)
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ip = IP(src='10.1.0.1', dst='10.2.0.1', flags=1, id=ip_id)
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l3hdrs.append(ip)
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# IPv4 with options
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ip = IP(src='10.1.0.1', dst='10.2.0.1', id=ip_id, options=[IPOption_MTU_Probe()])
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l3hdrs.append(ip)
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# IPv6
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ip6 = IPv6(src='fd12:3456:789a:1::1', dst='fd12:3456:789a:2::1', fl=ip_id)
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l3hdrs.append(ip6)
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# IPv6 with extensions (fragmented)
|
||||
ip6 = IPv6(src='fd12:3456:789a:1::1', dst='fd12:3456:789a:2::1', fl=ip_id)
|
||||
frag = IPv6ExtHdrFragment()
|
||||
l3hdrs.append(ip6 / frag)
|
||||
|
||||
# IPv6 with extensions
|
||||
ip6 = IPv6(src='fd12:3456:789a:1::1', dst='fd12:3456:789a:2::1', fl=ip_id)
|
||||
hbh = IPv6ExtHdrHopByHop(options=[RouterAlert()])
|
||||
l3hdrs.append(ip6 / hbh)
|
||||
|
||||
# IPv6 with extensions 2
|
||||
ip6 = IPv6(src='fd12:3456:789a:1::1', dst='fd12:3456:789a:2::1', fl=ip_id)
|
||||
hbh = IPv6ExtHdrHopByHop(options=[RouterAlert(), RouterAlert(), RouterAlert(), RouterAlert()])
|
||||
l3hdrs.append(ip6 / hbh)
|
||||
|
||||
for l3hdr in l3hdrs:
|
||||
|
||||
l3hdr = l3hdr.copy()
|
||||
if IP in l3hdr:
|
||||
l3hdr.id = ip_id
|
||||
if IPv6 in l3hdr:
|
||||
l3hdr.fl = ip_id
|
||||
|
||||
# IP (empty)
|
||||
if IP in l3hdr:
|
||||
hdr = l3hdr.copy()
|
||||
hdr.proto = 59
|
||||
test_pkts.append(l2hdr / hdr)
|
||||
else:
|
||||
test_pkts.append(l2hdr / l3hdr)
|
||||
|
||||
# IP (unsupported protocol)
|
||||
if IP in l3hdr:
|
||||
hdr = l3hdr.copy()
|
||||
hdr.proto = 59
|
||||
test_pkts.append(l2hdr / hdr / payload)
|
||||
else:
|
||||
test_pkts.append(l2hdr / l3hdr / payload)
|
||||
|
||||
if IP in l3hdr:
|
||||
# ICMP
|
||||
icmp = ICMP(type=8)
|
||||
test_pkts.append(l2hdr / l3hdr / icmp / payload)
|
||||
|
||||
if IPv6 in l3hdr:
|
||||
# ICMPv6 / NDP
|
||||
ns = ICMPv6ND_NS(tgt='::')
|
||||
test_pkts.append(l2hdr / l3hdr / ns)
|
||||
|
||||
# UDP (empty)
|
||||
udp = UDP(sport=ip_id, dport=0x1000+ip_id)
|
||||
test_pkts.append(l2hdr / l3hdr / udp)
|
||||
|
||||
# UDP
|
||||
udp = UDP(sport=ip_id, dport=0x1000+ip_id)
|
||||
test_pkts.append(l2hdr / l3hdr / udp / payload)
|
||||
|
||||
# TCP (empty)
|
||||
tcp = TCP(sport=ip_id, dport=0x1000+ip_id, seq=54321, ack=12345, window=8192)
|
||||
test_pkts.append(l2hdr / l3hdr / tcp)
|
||||
|
||||
# TCP with options (empty)
|
||||
tcp = TCP(sport=ip_id, dport=0x1000+ip_id, seq=54321, ack=12345, window=8192, options=[('Timestamp',(0,0))])
|
||||
test_pkts.append(l2hdr / l3hdr / tcp)
|
||||
|
||||
# TCP
|
||||
tcp = TCP(sport=ip_id, dport=0x1000+ip_id, seq=54321, ack=12345, window=8192)
|
||||
test_pkts.append(l2hdr / l3hdr / tcp / payload)
|
||||
|
||||
# TCP with options
|
||||
tcp = TCP(sport=ip_id, dport=0x1000+ip_id, seq=54321, ack=12345, window=8192, options=[('Timestamp',(0,0))])
|
||||
test_pkts.append(l2hdr / l3hdr / tcp / payload)
|
||||
|
||||
ip_id += 1
|
||||
|
||||
for pkt in test_pkts:
|
||||
tb.log.info("Packet: %r", pkt)
|
||||
|
||||
pkt_b = pkt.build()
|
||||
|
||||
rx_csum = ~scapy.utils.checksum(bytes(pkt_b[14:])) & 0xffff
|
||||
|
||||
await tb.pkt_source.send(AxiStreamFrame(pkt_b))
|
||||
|
||||
meta = await tb.meta_sink.recv()
|
||||
|
||||
tb.log.info("Metadata: %r", meta)
|
||||
|
||||
pkt_len, pkt_sum = struct.unpack_from('<HH', meta.tdata, 0)
|
||||
|
||||
tb.log.info("Payload length: %d", pkt_len)
|
||||
tb.log.info("Packet checksum: 0x%04x", pkt_sum)
|
||||
|
||||
assert pkt_len == len(pkt_b)
|
||||
assert pkt_sum == rx_csum
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
if cocotb.SIM_NAME:
|
||||
|
||||
factory = TestFactory(run_test)
|
||||
factory.generate_tests()
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'lib'))
|
||||
taxi_src_dir = os.path.abspath(os.path.join(lib_dir, 'taxi', 'src'))
|
||||
|
||||
|
||||
def process_f_files(files):
|
||||
lst = {}
|
||||
for f in files:
|
||||
if f[-2:].lower() == '.f':
|
||||
with open(f, 'r') as fp:
|
||||
l = fp.read().split()
|
||||
for f in process_f_files([os.path.join(os.path.dirname(f), x) for x in l]):
|
||||
lst[os.path.basename(f)] = f
|
||||
else:
|
||||
lst[os.path.basename(f)] = f
|
||||
return list(lst.values())
|
||||
|
||||
|
||||
def test_zircon_ip_len_cksum(request, data_w=32):
|
||||
dut = "zircon_ip_len_cksum"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = module
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(tests_dir, f"{toplevel}.sv"),
|
||||
os.path.join(rtl_dir, f"{dut}.sv"),
|
||||
os.path.join(taxi_src_dir, "axis", "rtl", "taxi_axis_if.sv"),
|
||||
]
|
||||
|
||||
verilog_sources = process_f_files(verilog_sources)
|
||||
|
||||
parameters = {}
|
||||
|
||||
parameters['DATA_W'] = data_w
|
||||
parameters['META_W'] = 32
|
||||
parameters['START_OFFSET'] = 14
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
simulator="verilator",
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
@@ -0,0 +1,56 @@
|
||||
// SPDX-License-Identifier: CERN-OHL-S-2.0
|
||||
/*
|
||||
|
||||
Copyright (c) 2025 FPGA Ninja, LLC
|
||||
|
||||
Authors:
|
||||
- Alex Forencich
|
||||
|
||||
*/
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* testbench
|
||||
*/
|
||||
module test_zircon_ip_len_cksum #
|
||||
(
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
parameter DATA_W = 32,
|
||||
parameter META_W = 32,
|
||||
parameter START_OFFSET = 14
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
)
|
||||
();
|
||||
|
||||
logic clk;
|
||||
logic rst;
|
||||
|
||||
taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(1)) s_axis_pkt();
|
||||
taxi_axis_if #(.DATA_W(DATA_W), .USER_EN(1), .USER_W(1)) m_axis_pkt();
|
||||
taxi_axis_if #(.DATA_W(META_W), .USER_EN(1), .USER_W(1)) m_axis_meta();
|
||||
|
||||
zircon_ip_len_cksum #(
|
||||
.START_OFFSET(START_OFFSET)
|
||||
)
|
||||
uut (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* Packet header input
|
||||
*/
|
||||
.s_axis_pkt(s_axis_pkt),
|
||||
.m_axis_pkt(m_axis_pkt),
|
||||
|
||||
/*
|
||||
* Packet metadata output
|
||||
*/
|
||||
.m_axis_meta(m_axis_meta)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Reference in New Issue
Block a user